Recall the project diagram from the last document:
In this checkpoint we will concerned with the yellow tinted blocks. The Marvell 88E1111 is a device on the XUPV5 (not within the FPGA itself) that implements the physical layer of the network interface. The Ethernet block is a module that will be instantiated on the FPGA and is analogous to the UART module you worked with for lab 5 and checkpoint 1 (albeit significantly more complex due to the packet-oriented nature of the Ethernet protocol).
Luckily for you, Xilinx provides an implementation of an Ethernet interface through coregen, so you won't have to worry about the messy details.
The project skeleton now provides a wrapper around the coregen interface that presents a very simplied set of signals for your processor to use. A description of each of the signals in the interface follows.
Clock
and Reset
do the obvious thingsDataIn
, DataInValid
, and DataInReady
provide an interface for sending
data similar to the UART module. Again, like in the UART, DataIn
is 8 bits
wide.DataOut
, DataOutValid
, and DataOutReady
are again similar to the same
signals in the UART.DataInStartFrame
& DataInEndFrame
are used begin or end a new Ethernet
packet. They are set at the same time the first byte in the packet or the
last byte in the packet is sent, respectively.DataOutStartFrame
& DataOutEndFrame
are used to signal the beginning and
end of receiveded packets.The memory map has been extended to give the CPU access to the Ethernet interface.
Address | Read/Write | Function |
---|---|---|
0xFFFF0000 |
Read | UART Receiver control |
0xFFFF0004 |
Read | UART Receiver data |
0xFFFF0008 |
Read | UART Transmitter control |
0xFFFF000C |
Write | UART Transmitter data |
0xFFFF0010 |
Read | ENET Receiver control |
0xFFFF0014 |
Read | ENET Receiver data |
0xFFFF0018 |
Read | ENET Transmitter control |
0xFFFF001C |
Write | ENET Transmitter data |
For the most part the Ethernet interface is identical to the UART interface,
however there is the small issue of the StartFrame
and EndFrame
signals.
Because the beginning and end of the frame are signaled at the same time that a
byte is either sent or received, there is a simple solution available to this
problem. We simply add the start and end signals as flags to the data signals.
Bits 0-7 contain the actual data byte, bit 8 is the StartFrame
flag, and bit
9 is the EndFrame
flag. This keeps the interface as simple as possible.
The reason for this checkpoint is to give you the capability to execute TFTP
transfers between your CPU and workstation. To facilitate this a TFTP client,
implemented in the BIOS150, is given as well as a TFTP daemon. The goal is to
be able to flash the FPGA with your CPU and the BIOS program, once it has been
flashed you may connect to the CPU with screen
over the serial connection.
This will present you with a prompt and allow you to enter commands, the most
interesting of which initiates a TFTP read.
Along with the Ethernet modules we are providing you with some useful software
for this checkpoint. It can be found in the bios150v2
directory. Be aware
that by default the stack is initialized to 0x8000(16384 words), your
memory must be deep enough to support this.When you run this program on
your CPU, it provides you with a prompt (over serial) and provides you with
the following commands:
Command | Function |
---|---|
get filename address |
Fetch filename using the TFTP protocol and store it's contents at address |
jal address |
Execute a jump to address |
sw , sb , sh data address |
Store data to address |
lw , lbu , lhu address |
Load from address |
You can use the tftpd
program on the workstations to serve files (such as
binaries you want to load in to your instruction memory) from your workstation
attached via Ethernet. The command to run is,
tftpd -a 169.254.1.1 -p 6969
To test the BIOS TFTP functionality, do the following,
tftpd -a 169.254.1.1 -p 6969
.screen
and connect to your CPU.get fpgadat 00010000
, this should issue a read
request to the TFTP server for the file named "fpgadat" and will attempt to
store the file starting at the address 0x00010000.Click here to view a wireshark dump of a complete TFTP transfer.
The following are things to check for correct behaviour
Finally, the most useful program will be wireshark
to run wireshark
,
execute the wireshark
command from the command line. Click "Run Unprivileged"
on the window that pops up, then click the "Capture" menu option, select
"Interfaces", and click the "Start" button next to the 169.254.1.1
ip
status line. This will allow you to view all packets being transferred on the
169.254.1.1
Ethernet connection. A helpful hint is to right click on packets,
and click "Decode As" and select TFTP from the list.
To be checked off for this checkpoint, you must show us that you can load files
from a tftp server running on the workstation, and view the memory through the
lw
command.