Computer Science 150: Components and Design Techniques for Digital Systems (5 Units)

Fall 2000

Previous Course Homepages

Fall 1996, Spring 1997, Fall 1997, Spring 1998, Fall 1998, Spring 1999, Fall 1999, Spring 2000.

What's New

• 10 December 2000: Parts/board return 1-3 PM, Monday, 11 December, Tuesday, 12 December, in the CS 150 Lab, Cory Hall. PLEASE BREAK DOWN YOUR BOARDS BEFORE COMING TO THE LAB TO RETURN THEM!
• 10 December 2000: Final Examination Thursday, 14 December, 12:30-3:30 PM, in 230 Hearst Gym. Open book/open note. Please bring your own blue books!
• 6 September 2000: Lecture videotapes available in 205 McLaughlin Hall.

Table of Contents

• Catalog Description
• Course Information (Goals, Syllabus, Times and Locations, Textbook, Grading)
• Course Staff (Instructor, Teaching Assistants, Readers)
• Course Calendar (Draft, Detailed)
• Homework Policy, Lab Policy, Public Discussion
• Technical Discussion

Catalog Description

CS 150. Components and Design Techniques for Digital Systems. (5) Three hours of lecture, one hour of discussion, and three hours of laboratory per week. Prerequisites: 61C, Electrical Engineering 40 or 42. Basic building blocks and design methods to contruct synchronous digital systems. Alternative representations for digital systems. Bipolar TTL vs. MOS implementation technologies. Standard logic (SSI, MSI) vs. programmable logic (PLD, PGA). Finite state machine design. Digital computer building blocks as case studies. Introduction to computer-aided design software. Formal hardware laboratories and substantial design project. Informal software laboratory periodically throughout semester. (F,SP) Katz, Newton, Pister.

Course Goals

• Understand digital logic at the gate and switch level including both combinational and sequential logic elements.
• Understand clocking methodologies to manage information flow and preservation of circuit state.
• Appreciate digital logic specification methods and the compilation process that transforms these into logic networks.
• Gaim experience with computer-aided design tools for implementation with programmable logic devices.
• Appreciate the advantages/disadvantages between hardware and software implementations of a function.

Course Syllabus

1. Introduction to modern digital logic design
2. Combinational logic
   • Switch logic and basic gates
   • Boolean algebra
   • Two-level logic
   • Regular logic structures
   • Multi-level networks and transformations
   • Programmable logic devices
   • Time response
   • Case studies
3. Sequential logic
   • Networks with feedback
   • Basic latches and flip-flops
   • Timing methodologies
   • Registers and counters
   • Programmable logic devices
   • Case studies
4. Finite state machine design
   • Concepts of FSMs
   • Basic design approach
   • Specification methods
   • State minimization
   • State encoding
   • FSM partitioning
   • Implementation of FSMs
   • Programmable logic devices
   • Case studies
5. Elements of computers
   • Arithmetic circuits
   • Arithmetic and logic units
   • Register and bus structures
   • Controllers/Sequencers
   • Microprogramming
6. Computer-aided design tools for logic design
   • Schematic entry
   • State diagram entry
   • Hardware description language entry
   • Compilation to logic networks
   • Simulation
   • Mapping to programmable logic devices
7. Practical topics
   • Non-gate logic
   • Asynchronous inputs and metastability
   • Memories: RAM and ROM
   • Implementation technologies

Course Times and Locations

Lecture: T, Th 2:00-3:30, 10 Evans
Discussions: M 1-2 (285 Cory), Tu 1-2 (310 Soda), W 1-2 (71 Evans), W 2-3 (4 Evans), Th 1-2 (310 Soda)
Laboratory Lecture: F 2:00-3:00, 10 Evans
Laboratories: M, Tu, W 9:00-12:00 and M, Tu, W, Th 5:00-8:00 PM, Make-Up: F 9-11:30 AM, New! M 1-4 PM (all in 204B Cory Hall)

Course Textbook

R. H. Katz, Contemporary Logic Design, Addison Wesley Publishing Company, Reading, MA, 1993.

New evolving draft of a second edition (rough and incomplete)

Course Grading

• Homeworks: 10%
• Laboratories: 20%
• Midterms (2): 20%
• Final Project: 30%
• Final Exam: 20%

Course Instructor

Professor Randy H. Katz, Computer Science Division, EECS Department, 637 Soda Hall, 510-642-8778.
Office Hours: Th 12:00-2:00 PM and by appointment. E-mail: randy@cs.Berkeley.edu

Teaching Assistants

• Head TA: Norm Zhou (normzhou@cs.Berkeley.edu); Office Hours: Th 3:30-4:30, 204B Cory
• Jeff Du (ydu@uclink4.berkeley.edu); Office Hours: W 2-3, 204B Cory
• Ramki Gummadi (ramki@cs.Berkeley.edu); Office Hours: F 9:30-11:30, 4th Floor Soda Lounge
• Jimmy Su (jimmysu@cory.eecs.berkeley.edu); Office Hours: T 4-5, 204B Cory
• Sammy Sy (sammysy@uclink4.berkeley.edu); Office Hours: Th 12:30-1:30, 204B Cory
• Lakme Subramanian (lakme@cs.Berkeley.edu); Office Hours: M 4-5, 4th Floor Soda Lounge
• Laura Todd (laranth@cory.eecs.berkeley.edu); Office Hours: W 4-5, 204B Cory
• Jeff Tsai (jmtsai@cory.eecs.Berkeley.edu); Office Hours: W 4-5, 204B Cory
• PoYan (neewok@uclink4.berkeley.edu); Office Hours: Th 1-2, 204B Cory

Readers

• Eugene Chu (ugenechu@uclink4.berkeley.edu)
• Binh Ho (binhh@cory.eecs.Berkeley.edu)
• Kai Pong Lei (kaipong@cory.eecs.berkeley.edu)

Draft Course Calendar

• 8/29      First Lecture
• 9/1        First Lab Lecture
• 9/5        First Lab
• Midterms during Weeks 5 (9/26, 9/28) and 10 (10/20, 11/2)
• 11/23-4 Thanksgivings Holiday
• 12/7      Last Lecture
• 12/14    Final Exam 12:30-3:30 (Arrange your Christmas break travel plans appropriately!)

(Tentative) Detailed Course Calendar

Week #1

29 August: Course Administration and Overview

31 August: Course Introduction

1 September: Laboratory Administration and Overview, Introduction to Lab #1

Readings: CLD, Chapter 1

Lecture Materials (ppt, pdf)

Problem Set #1 Due 8 September: (word97, pdf)

Problem Set #1 Solutions (word97, pdf)

Week #2

5 September: Combinational Logic

7 September: Combinational Logic

8 September: Introduction to Lab #2

Laboratory #1: Schematic Entry and Simulation, Part I (word97, pdf)

Readings: CLD 2.1, 2.2, 2.3, 3.1

Lecture Materials (ppt, pdf)

Lab Lecture Materials (pdf)

Problem Set #2 Due 15 September: (word97, pdf)

Problem Set #2 Solutions (word97, pdf)

Homework Quiz #1 Solutions (word97, pdf)

Week #3

12 September: Combinational Logic Implementation

14 September: Combinational Logic Implementation

15 September: Introduction to Lab #3

Laboratory #2: Schematic Entry and Simulation, Part II--FSMs (word97, pdf)

Readings: CLD 2.4, 3.3, 3.4, 4.1, 4.2

Lecture Materials (ppt, pdf)

Lab Lecture Materials (pdf)

Problem Set #3 Due 22 September: (word97, pdf)

Problem Set #3 Solutions Part 1 (word97, pdf), Part 2 (word97, pdf)

Solutions to HW Quiz #2 (word97, pdf)

Week #4

19 September: Combinational Logic Examples

21 September: Combinational Logic Examples

22 September: Introduction to Lab #4

Laboratory #3: Field Programmable Gate Arrays (FPGAs)/FSMs (word97, pdf)

Readings: CLD 4.3, 4.4, 4.5, 4.6, 4.7

Lecture Materials (ppt, pdf)

Problem Set #4 Due 29 September: (word97, pdf)

Problem Set #4 Solutions (word97, pdf)

Solutions to HW Quiz #3 (word97, pdf)

Week #5

26 September: Review for Midterm I--Combinational Logic

28 September: Midterm I--Combinational Logic

29 September: Introduction to Laboratory #5

Laboratory #4: Introduction to Test Equipment (word97, pdf)

Solutions to HW Quiz #4 (word97, pdf)

NO Problem Set this week! Study for exam.

Week #6

3 October: Hardware Description Languages

5 October: Sequential Logic

Lecture Materials (ppt, pdf)

6 October: Introduction to Laboratory #6

Laboratory #5: Shift Registers and Counters (pdf)

Laboratory Lecture Materials (ppt, pdf)

Readings: CLD 6.1, 6.2

Problem Set #5 Due 13 October: (word97, pdf)

Problem Set #5 Solutions (word97, pdf)

Solutions to HW Quiz #5 (word97, pdf)

Week #7

10 October: Sequential Logic

12 October: Sequential Logic Implementation

Lecture Materials (ppt, pdf)

13 October: Introduction to Project Checkpoint #1

Laboratory #6: Nasty Realities (word97, pdf)

Laboratory Lecture Materials (ppt, pdf)

Readings: CLD 6.3, 6.4, 7.1, 7.2, 7.5, 7.6

Problem Set #6 Due 20 October: (word97, pdf)

Problem Set #6 Solutions Part A (word97, pdf) Part B (word97, pdf)

Solutions to HW Quiz #6 (pdf)

Week #8

17 October: Sequential Logic Implementation

19 October: Sequential Logic Examples

Lecture Materials (ppt, pdf)

20 October: Introduction to Project Checkpoint #2

Project Checkpoint #1: Wirewrap, SRAM, and FIFO Design (word97, pdf)

Laboratory Lecture Materials (ppt, pdf)

Readings: CLD 8.1, 8.2, 8.3, 8.4, 8.5

Problem Set #7 Due 27 October: (word97, pdf)

Problem Set #7 Solutions Part A (word97, pdf), Part B (word97, pdf)

Solutions to HW Quiz #7 (word97, pdf)

Week #9

24 October: Sequential Logic Examples

26 October: Basic Computer Organization

Lecture Materials (ppt, pdf)

27 October: Introduction to Project Checkpoint #3

Project Checkpoint #2: UART Transmitter/Receiver (word97, pdf)

Laboratory Lecture Materials (ppt, pdf)

Readings: CLD 10.1, 10.2, 10.3, 10.4, 11.1

NO Problem Set this week! Study for exam.

Week #10

31 October: Final Project Overview and Checkpoint #4

Final Project Information (ppt, pdf)

Exam Review (ppt, pdf)

2 November: Midterm II--Sequential Logic

Project Checkpoint #3: Audio Interfaces (word97, pdf)

Laboratory Lecture Materials (ppt, pdf)

Readings:

Problem Set #8/9, Double Problem Set, Due 17 November: (word97, pdf)

Problem Set #8/9 Solutions, Part A (word97, pdf), Part B (word97, pdf)

Week #11

7 November: Basic Computer Organization

9 November: Arithmetic Circuits

Lecture Materials (ppt, pdf)

Project Checkpoint #4 (word97, pdf)

Readings: CLD 11.2, 11.3, 11.4, 5.1, 5.2

Week #12

14 November: Arithmetic Circuits

16 November: Computer Implementation

Lecture Materials (ppt, pdf)

17 November: Final Project Report Requirements

Lab Lecture Materials (word97, pdf)

More Lab Lecture Materials (ppt, pdf)

Readings: CLD 5.3, 5.4, 5.5, 5.6

Problem Set #10/11, Double Problem Set, Due 1 December (pdf)

Problem Set #10/11, Part 1 Solution (pdf), Part 2 Solution (word97, pdf), Part 3 Solution (word97, pdf)

Week #13

21 November: Computer Implementation

Early Final Project Demos (Thanksgivings Bonus!)

Readings: CLD 12.1, 12.2, 12.5

Week #14

28 November: Special Topics--FPGA Evolution

Lecture Materials (ppt, pdf)

More Lecture Materials (ppt, pdf)

30 November: Special Topics--Hardware Description Languages/CAD Tools

Lecture Materials (ppt, pdf)

Final Project Demonstration Deadline (Friday, December 1)

Week #15

5 December: Course Review and Summary

7 December: Course Wrap-up and Evaluation

Final Project Reports Due/Late Demonstration Penalty (Friday, December 8)

Homework and Examination Regrade Policies

• Assignments are distributed on Thursdays, collected the following Friday at noon
• Submit assignments to CS150 homework box, on door of Cory 218
• Homework is graded on effort, not correctness
• See calendar on this web page for handouts
  
• Please attend a discussion section to hear about the solutions to the exam. This will usually take place during the week following the return of the exam.
• Regrades are by written petition only. The petition should succinctly state why you believe that your solution is correct when we believed it to be wrong. These should be given to the instructor.

Public Discussion

• Post/receive announcements, questions, and discussion
• UseNet news group:  ucb.class.cs150
• student e-mail list:  eecs150@cory.eecs.berkeley.edu (please use judiciously!)

Technical Documentation

• Xilinx Foundation 2.1 online manuals -- (fast, searchable web interface to all Xilinx docs)
• Xilinx Library Guide -- (PDF 9MB)
• Xilinx XC4000E / XC4000X -- data sheet (PDF 727KB)
• STMicroelectronics M27C4001 EPROM -- data sheet (PDF), wrap-ID (TeX, PDF)
• Motorola MOC5009 Optoisolator -- data sheet (PDF), wrap-ID (TeX, PDF)
• Analog Devices AD1866 DAC -- data sheet (PDF), wrap-ID (TeX, PDF)
• National Semiconductor LM4862 "Boomer" audio amplifier -- data sheet (PDF), wrap-ID (TeX, PDF)