//----------------------------------------------------------------------- // FPGA_TOP.v // **** Version 23 Sep 2003 always make sure you are using latest version **** // Top level interface from a Xilinx V2000-E FG680 FPGA // to U.C. Berkeley CalLinx board. // Includes code for TFTP manipulation of onboard SDRAM //----------------------------------------------------------------------- //----------------------------------------------------------------------- // Module: FPGA_TOP // Desc: This is the root module on the VirtexE XCV2000E chip on // the CalLinx board. This includes all of the pin // assignments and I/O. //----------------------------------------------------------------------- module FPGA_TOP ( //------------------------------------------------------- // RJ45 LEDs [Bank 2 Left Top] //------------------------------------------------------- RJ45_TRC_, // OUT(2b), LEDs on the Top Right RJ45_BRC_, // OUT(2b), LEDs on the Bottom Right RJ45_TLC_, // OUT(2b), LEDs on the Top Left RJ45_BLC_, // OUT(2b), LEDs on the Bottom Left //------------------------------------------------------- //------------------------------------------------------- // Ethernet Physical Layer [Bank 0,1 Top] //------------------------------------------------------- // These signals provide a serial readout of the Ethernet // chips LED outputs. The chip will drive the PHY_LEDENA // output high and then clock out 24bits of LED status // data, driving both PHY_LEDDAT and PHY_LEDCLK PHY_LEDCLK_, // IN(1b), Clock PHY_LEDDAT_, // IN(1b), Data PHY_LEDENA_, // IN(1b), Enable PHY_ADD_, // OUT(3b), Address set (0 for CalLinx) PHY_MDIO_, // INOUT(1b), MII Data Bus PHY_MDINT_, // IN(1b), MII Control Interrupt PHY_MDC_, // OUT(1b), MII Clock PHY_MDDIS_, // OUT(1b), MII Disable PHY_PWRDN_, // OUT(1b), Powerdown Control PHY_RESET_, // OUT(1b), Active Low Reset PHY_FDE_, // OUT(1b) PHY_AUTOENA_, // OUT(1b) PHY_BYPSCR_, // OUT(1b) PHY_CFG_, // OUT(3b), Phy Chip config lines PHY_LED0_, // IN(3b), LEDs for port 0 PHY_LED1_, // IN(3b), LEDs for port 1 PHY_LED2_, // IN(3b), LEDs for port 2 PHY_LED3_, // IN(3b), LEDs for port 3 PHY_RXD0_, // IN(4b), Receive Data port 0 PHY_RXD1_, // IN(4b), Receive Data port 1 PHY_RXD2_, // IN(4b), Receive Data port 2 PHY_RXD3_, // IN(4b), Receive Data port 3 PHY_RX_DV_, // IN(4b), Receive Data Valid[Port] PHY_RX_CLK_, // IN(4b), Receive Data Clock[Port] PHY_RX_ER_, // IN(4b), Receive Error[Port] PHY_TX_ER_, // OUT(4b), Transmit Error[Port] PHY_TX_CLK_, // IN(4b), Transmit Data Clock[Port] PHY_TX_EN_, // OUT(4b), Transmit Data Clock[Port] PHY_TXD0_, // OUT(4b), Transmit Data port 0 PHY_TXD1_, // OUT(4b), Transmit Data port 1 PHY_TXD2_, // OUT(4b), Transmit Data port 2 PHY_TXD3_, // OUT(4b), Transmit Data port 4 PHY_COL_, // IN(4b), Collision Detect PHY_CRS_, // IN(4b), Carrier Sense PHY_TRSTE_, // OUT(4b), Tristate Control[Port] //------------------------------------------------------- //------------------------------------------------------- // Audio Codec [Bank 1 Top-Left] //------------------------------------------------------- AP_SDATA_OUT_, AP_BIT_CLOCK_, AP_SDATA_IN_, AP_SYNC_, AP_RESET_B_, AP_PC_BEEP_, AA_MUTE_, // Audio Amp Mute //------------------------------------------------------- //------------------------------------------------------- // SDRAM [Bank 7 Top-Right] //------------------------------------------------------- RAM_DQ_, // INOUT(32b), Data Bus RAM_CLK_, // OUT(1b), Clock RAM_CLKE_, // OUT(1b), Clock Enable RAM_DQMH_, RAM_DQML_, // These signals are used to specify the SDRAM action RAM_CS_, // OUT(1b), Chip Select RAM_RAS_, // OUT(1b), Row Address Select RAM_CAS_, // OUT(1b), Column Address Select RAM_WE_, // OUT(1b), Write Enable RAM_BA_, // OUT(2b), Bank Address RAM_A_, // OUT(12b), Address //------------------------------------------------------- //------------------------------------------------------- // Buttons and DIPSwitches [Bank 7,6 Right] //------------------------------------------------------- SW9_, // IN(8b), Active Low DIP Switch #9 SW10_, // IN(8b), Active Low DIP Switch #10 SW_, // IN(8b), Active Low Push Buttons //------------------------------------------------------- //------------------------------------------------------- // System ACE Chip [Bank 2 Left-Top] //------------------------------------------------------- ACE_MPBRDY_, ACE_MPIRQ_, ACE_MPCE_B_, ACE_MPWE_B_, ACE_MPOE_B_, ACE_MPA_, // (7b) ACE_MPD_, // (16b) //------------------------------------------------------- //------------------------------------------------------- // Video Encoder [Bank 3 Left-Bottom] //------------------------------------------------------- VE_P_, // (10b) VE_SCLK_, VE_SDA_, VE_PAL_NTSC_, VE_RESET_B_, VE_HSYNC_B_, VE_VSYNC_B_, VE_BLANK_B_, VE_SCRESET_, VE_CLOCK_, // Clock VE_CLKIN_, //------------------------------------------------------- //------------------------------------------------------- // Video Decoder [Bank 3 Left-Bottom] //------------------------------------------------------- VD_CHAN1_LLC_, // (2b) VD_CHAN1_DATA_, // (10b) VD_CHAN1_I2C_CLOCK_, VD_CHAN1_I2C_DATA_, VD_CHAN1_ISO_, VD_RESET_B_, //------------------------------------------------------- //------------------------------------------------------- // General Purpose LEDs //------------------------------------------------------- LED_, // OUT(8b), Active LOW //------------------------------------------------------- //------------------------------------------------------- // 7 Segment LEDs x8 [Bank 4,5 Bottom] //------------------------------------------------------- SEG1_, // OUT(7b), Active High (MSb is Seg 'a') SEG2_, // OUT(7b), Active High (MSb is Seg 'a') SEG3_, // OUT(7b), Active High (MSb is Seg 'a') SEG4_, // OUT(7b), Active High (MSb is Seg 'a') SEG5_, // OUT(7b), Active High (MSb is Seg 'a') SEG6_, // OUT(7b), Active High (MSb is Seg 'a') SEG7_, // OUT(7b), Active High (MSb is Seg 'a') SEG8_, // OUT(7b), Active High (MSb is Seg 'a') SEG_POINT_, // OUT(8b), Active High (MSb is SEG8_) SEG_COM_, // OUT(8b), Active Low (MSb is SEG8_) //------------------------------------------------------- //------------------------------------------------------- // Test-Point Headers Around FPGA //------------------------------------------------------- PINOUT_TOP_CLOSE_, PINOUT_TOP_FAR_, PINOUT_LEFT_CLOSE_, PINOUT_LEFT_FAR_, PINOUT_BOTTOM_CLOSE_, PINOUT_BOTTOM_FAR_, PINOUT_RIGHT_CLOSE_, PINOUT_RIGHT_FAR_ //------------------------------------------------------- ); //--------------------------------------------------------------- // RJ45 LEDs //--------------------------------------------------------------- output [2:1] RJ45_TRC_ /*synthesis xc_loc = "E1,D3"*/; output [2:1] RJ45_BRC_ /*synthesis xc_loc = "F1,E2"*/; output [2:1] RJ45_TLC_ /*synthesis xc_loc = "F3,F2"*/; output [2:1] RJ45_BLC_ /*synthesis xc_loc = "G1,F4"*/; //--------------------------------------------------------------- //--------------------------------------------------------------- // Ethernet Physical Layer //--------------------------------------------------------------- input PHY_LEDCLK_ /*synthesis xc_loc = "D14"*/; input PHY_LEDDAT_ /*synthesis xc_loc = "A15"*/; input PHY_LEDENA_ /*synthesis xc_loc = "B15"*/; output [4:2] PHY_ADD_ /*synthesis xc_loc = "A16,D15,C15"*/; //inout PHY_MDIO_; input PHY_MDIO_ /*synthesis xc_loc = "B32"*/; input PHY_MDINT_ /*synthesis xc_loc = "A32"*/; output PHY_MDC_ /*synthesis xc_loc = "D33"*/; output PHY_MDDIS_ /*synthesis xc_loc = "C33"*/; output PHY_PWRDN_ /*synthesis xc_loc = "B33"*/; output PHY_RESET_ /*synthesis xc_loc = "A34"*/; output PHY_FDE_ /*synthesis xc_loc = "D35"*/; output PHY_AUTOENA_ /*synthesis xc_loc = "C35"*/; output PHY_BYPSCR_ /*synthesis xc_loc = "B35"*/; output [2:0] PHY_CFG_ /*synthesis xc_loc = "A35,B36,A36"*/; input [2:0] PHY_LED0_ /*synthesis xc_pullup = 1 xc_loc = "C14,B14,A14"*/; input [2:0] PHY_LED1_ /*synthesis xc_pullup = 1 xc_loc = "D13,C13,B13"*/; input [2:0] PHY_LED2_ /*synthesis xc_pullup = 1 xc_loc = "A13,C12,B12"*/; input [2:0] PHY_LED3_ /*synthesis xc_pullup = 1 xc_loc = "A12,D11,C11"*/; input [3:0] PHY_RXD0_ /*synthesis xc_loc = "B16,C16,D16,A17"*/; input [3:0] PHY_RXD1_ /*synthesis xc_loc = "D19,C21,B20,B21"*/; input [3:0] PHY_RXD2_ /*synthesis xc_loc = "C24,B24,A24,D25"*/; input [3:0] PHY_RXD3_ /*synthesis xc_loc = "B28,A28,D29,C29"*/; input [3:0] PHY_RX_DV_ /*synthesis xc_loc = "B29,C25,A21,B17"*/; input [3:0] PHY_RX_CLK_ /*synthesis syn_noclockbuf = 1 xc_loc = "A29,B25,E22,C17"*/; input [3:0] PHY_RX_ER_ /*synthesis xc_loc = "D30,A25,D22,D17"*/; output [3:0] PHY_TX_ER_ /*synthesis xc_loc = "C30,D26,C22,E17"*/; input [3:0] PHY_TX_CLK_ /*synthesis syn_noclockbuf = 1 xc_loc = "B30,C26,B22,A18"*/; output [3:0] PHY_TX_EN_ /*synthesis xc_loc = "A30,B26,A22,B18"*/; output [3:0] PHY_TXD0_ /*synthesis xc_loc = "A19,E18,D18,C18"*/; output [3:0] PHY_TXD1_ /*synthesis xc_loc = "B23,C23,D23,E23"*/; output [3:0] PHY_TXD2_ /*synthesis xc_loc = "A26,D27,C27,B27"*/; output [3:0] PHY_TXD3_ /*synthesis xc_loc = "A31,B31,C31,D31"*/; input [3:0] PHY_COL_ /*synthesis xc_loc = "D32,A27,A23,B19"*/; input [3:0] PHY_CRS_ /*synthesis xc_loc = "C32,C28,D24,C19"*/; output [3:0] PHY_TRSTE_ /*synthesis xc_loc = "A33,D34,C34,B34"*/; //--------------------------------------------------------------- //--------------------------------------------------------------- // Audio Codec //--------------------------------------------------------------- input AP_SDATA_OUT_ /*synthesis xc_loc = "A4"*/; input AP_BIT_CLOCK_ /*synthesis xc_loc = "A5"*/; output AP_SDATA_IN_ /*synthesis xc_loc = "B5"*/; output AP_SYNC_ /*synthesis xc_loc = "C5"*/; output AP_RESET_B_ /*synthesis xc_loc = "A6"*/; output AP_PC_BEEP_ /*synthesis xc_loc = "B6"*/; output AA_MUTE_ /*synthesis xc_loc = "D1"*/; //--------------------------------------------------------------- //--------------------------------------------------------------- // SDRAM //--------------------------------------------------------------- inout [31:0] RAM_DQ_ /*synthesis xc_loc = "L36,L37,L38,L39,K36,K37,K38,K39,J36,J37,J38,J39,H36,H37,H38,H39,G36,G37,G38,G39,F36,F37,F38,F39,E37,E38,E39,D37,D38,D39,C38,B37"*/; output RAM_CLK_ /*synthesis xc_loc = "M39"*/; output RAM_CLKE_ /*synthesis xc_loc = "M38"*/; output RAM_DQMH_ /*synthesis xc_loc = "M37"*/; output RAM_DQML_ /*synthesis xc_loc = "N39"*/; output RAM_CS_ /*synthesis xc_loc = "N38"*/; output RAM_RAS_ /*synthesis xc_loc = "N37"*/; output RAM_CAS_ /*synthesis xc_loc = "N36"*/; output RAM_WE_ /*synthesis xc_loc = "P39"*/; output [1:0] RAM_BA_ /*synthesis xc_loc = "P38,P37"*/; output [11:0] RAM_A_ /*synthesis xc_loc = "U37,U38,U39,T36,T37,T38,T39,R36,R37,R38,R39,P36"*/; //--------------------------------------------------------------- //--------------------------------------------------------------- // Buttons and DIP Switches //--------------------------------------------------------------- input [8:1] SW9_ /*synthesis xc_loc = "AD36,AC39,AC38,AC37,AC36,AC35,AB39,AB38"*/; input [8:1] SW10_ /*synthesis xc_loc = "AF36,AE39,AE38,AE37,AE36,AD39,AD38,AD37"*/; input [8:1] SW_ /*synthesis xc_loc = "AB37,AB36,AB35,AA39,AA38,AA36,Y39,Y38"*/; //--------------------------------------------------------------- //--------------------------------------------------------------- // System ACE Chip //--------------------------------------------------------------- input ACE_MPBRDY_ /*synthesis xc_loc = "M2"*/; output ACE_MPIRQ_ /*synthesis xc_loc = "M3"*/; output ACE_MPCE_B_ /*synthesis xc_loc = "N1"*/; output ACE_MPWE_B_ /*synthesis xc_loc = "N2"*/; output ACE_MPOE_B_ /*synthesis xc_loc = "N3"*/; output [6:0] ACE_MPA_ /*synthesis xc_loc = "T1,R4,R3,R2,P2,P1,N4"*/; inout [15:0] ACE_MPD_ /*synthesis xc_loc = "W4,W3,W2,V5,V4,V3,V2,V1,U5,U4,U3,U2,U1,T4,T3,T2"*/; //--------------------------------------------------------------- //--------------------------------------------------------------- // Video Encoder //--------------------------------------------------------------- output [9:0] VE_P_ /*synthesis xc_loc = "AM3,AM4,AL1,AL2,AL3,AL4,AK1,AK2,AK3,AK4"*/; output VE_SCLK_ /*synthesis xc_loc = "AM2"*/; output VE_SDA_ /*synthesis xc_loc = "AM1"*/; output VE_PAL_NTSC_ /*synthesis xc_loc = "AN4"*/; output VE_RESET_B_ /*synthesis xc_loc = "AN3"*/; output VE_HSYNC_B_ /*synthesis xc_loc = "AN2"*/; output VE_VSYNC_B_ /*synthesis xc_loc = "AN1"*/; output VE_BLANK_B_ /*synthesis xc_loc = "AP4"*/; output VE_SCRESET_ /*synthesis xc_loc = "AP3"*/; input VE_CLOCK_ /*synthesis xc_loc = "A20"*/; output VE_CLKIN_ /*synthesis xc_loc = "AP2"*/; //--------------------------------------------------------------- //--------------------------------------------------------------- // Video Decoder //--------------------------------------------------------------- input [2:1] VD_CHAN1_LLC_; /*synthesis xc_loc = "AA3,AB2"*/ input [9:0] VD_CHAN1_DATA_; /*synthesis xc_loc = "AC5,AB1,AB3,AB4,AB5,AA1,AA2,Y1,Y2,W1"*/ output VD_CHAN1_I2C_CLOCK_; /*synthesis xc_loc = "AC4"*/ output VD_CHAN1_I2C_DATA_; /*synthesis xc_loc = "AC3"*/ output VD_CHAN1_ISO_; /*synthesis xc_loc = "AC2"*/ output VD_RESET_B_; /*synthesis xc_loc = "AC1"*/ //--------------------------------------------------------------- //--------------------------------------------------------------- // General Purpose LEDs //--------------------------------------------------------------- output [8:1] LED_ /*synthesis xc_loc = "W38,V35,V36,V37,V38,V39,U35,U36"*/; //--------------------------------------------------------------- //--------------------------------------------------------------- // 7 segment LEDs x8 //--------------------------------------------------------------- output [6:0] SEG1_ /*synthesis xc_loc = "AV8,AW8,AU8,AT8,AV9,AU9,AT9"*/; output [6:0] SEG2_ /*synthesis xc_loc = "AU10,AV10,AT10,AW11,AU11,AT11,AW12"*/; output [6:0] SEG3_ /*synthesis xc_loc = "AT18,AR18,AU18,AV18,AR17,AT17,AU17"*/; output [6:0] SEG4_ /*synthesis xc_loc = "AU21,AT19,AT21,AV20,AV21,AW21,AR22"*/; output [6:0] SEG5_ /*synthesis xc_loc = "AW28,AT29,AV28,AU28,AV27,AU27,AT27"*/; output [6:0] SEG6_ /*synthesis xc_loc = "AT31,AU31,AW30,AV30,AT30,AW29,AV29"*/; output [6:0] SEG7_ /*synthesis xc_loc = "AU33,AV33,AT33,AW32,AU32,AT32,AW31"*/; output [6:0] SEG8_ /*synthesis xc_loc = "AU36,AV36,AW35,AV35,AV34,AU34,AT34"*/; output [8:1] SEG_POINT_ /*synthesis xc_loc = "AW34,AV32,AU30,AW27,AW20,AW18,AV11,AW9"*/; output [8:1] SEG_COM_ /*synthesis xc_loc = "AW36,AW33,AV31,AU29,AU19,AV19,AW10,AT7"*/; //--------------------------------------------------------------- //--------------------------------------------------------------- output [19:0] PINOUT_TOP_CLOSE_ /*synthesis xc_loc = "C6,D6,A7,B7,C7,D7,A8,B8,C8,D8,A9,B9,C9,D9,A10,B10,C10,D10,A11,B11" */; output [19:0] PINOUT_TOP_FAR_ /*synthesis xc_loc = "M1,L4,L3,L2,L1,K4,K3,K2,K1,J4,J3,J2,J1,H4,H3,H2,H1,G4,G3,G2"*/; output [19:0] PINOUT_LEFT_CLOSE_ /*synthesis xc_loc = "AP1,AR3,AR2,AR1,AT3,AT2,AT1,AV3,AW4,AV4,AU4,AW5,AV5,AW6,AV6,AU6,AT6,AW7,AV7,AU7"*/; output [19:0] PINOUT_LEFT_FAR_ /*synthesis xc_loc = "AD4,AD2,AD1,AE4,AE3,AE2,AE1,AF4,AF3,AF2,AF1,AG4,AG3,AG1,AH3,AH2,AJ4,AJ3,AJ2,AJ1"*/; output [19:0] PINOUT_BOTTOM_CLOSE_ /*synthesis xc_loc = "AT22,AV22,AW22,AR23,AT23,AU23,AV23,AW23,AT24,AU24,AV24,AW24,AT25,AU25,AV25,AW25,AT26,AU26,AV26,AW26"*/; output [19:0] PINOUT_BOTTOM_FAR_ /*synthesis xc_loc = "AV12,AU12,AW13,AV13,AU13,AT13,AW14,AV14,AU14,AT14,AW15,AV15,AU15,AT15,AW16,AV16,AU16,AT16,AW17,AV17"*/; output [19:0] PINOUT_RIGHT_CLOSE_ /*synthesis xc_loc = "AL38,AL39,AM36,AM37,AM38,AM39,AN36,AN37,AN38,AN39,AP36,AP37,AP38,AP39,AR36,AR37,AR38,AR39,AT38,AT39"*/; output [19:0] PINOUT_RIGHT_FAR_ /*synthesis xc_loc = "AF37,AF38,AF39,AG36,AG37,AG38,AG39,AH37,AH38,AH39,AJ36,AJ37,AJ38,AJ39,AK36,AK37,AK38,AK39,AL36,AL37"*/; //--------------------------------------------------------------- endmodule