//----------------------------------------------------------------------- // // Video Encoder Skeleton // // Author: Alex Krasnov // Date: 10.13.2003 // Notes: Implements I2C // // Edit: Greg Gibeling // Date: 10.15.2003 // //----------------------------------------------------------------------- module vid_enc (CLK, RST, EN, DATA_IN, RST_OUT_, PAL_NTSC, HSYNC_, VSYNC_, BLANK_, SCRESET, P, SCLK, SDA); //--------------------------------------------------------------- // General Control Inputs //--------------------------------------------------------------- input CLK; // Clock input RST; // Reset input EN; // Enable //--------------------------------------------------------------- //--------------------------------------------------------------- // Video Input //--------------------------------------------------------------- input [31:0] DATA_IN; // Video data in from FIFO //--------------------------------------------------------------- //--------------------------------------------------------------- // Outputs to video encoder //--------------------------------------------------------------- output RST_OUT_; // General Control Outputs output PAL_NTSC; output HSYNC_; output VSYNC_; output BLANK_; output SCRESET; output [9:0] P; // Video data output SCLK; // I2C interface output SDA; //--------------------------------------------------------------- //--------------------------------------------------------------- // Wires //--------------------------------------------------------------- wire _SCLK; wire STOP, ACTIVE; wire [12:0] HCOUNT; //--------------------------------------------------------------- //--------------------------------------------------------------- // Sequential Logic (Registers) //--------------------------------------------------------------- rsff #(1) rsff(.C(CLK), .R(RST), .S(STOP), .Q(ACTIVE)); counter #(13) hc(.C(CLK), .R(RST), .E(EN), .O(HCOUNT), .TC(), .EO()); SRL64E srl(.C(_SCLK), .E(1'b1), .D(SDA), .Q(SDA)); defparam srl.INIT_00 = 16'b0000000000111111; defparam srl.INIT_01 = 16'b0110000001111000; defparam srl.INIT_02 = 16'b0000000000000000; defparam srl.INIT_03 = 16'b1100011001100110; //--------------------------------------------------------------- //--------------------------------------------------------------- // Simple Combinational Logic //--------------------------------------------------------------- assign SCLK = (EN & ~ACTIVE & HCOUNT[6]); // use shared counter assign _SCLK = (EN & ~ACTIVE & HCOUNT[5]); assign STOP = (HCOUNT[12:6] == 7'd64); //--------------------------------------------------------------- //--------------------------------------------------------------- //--------------------------------------------------------------- // Add your code here //--------------------------------------------------------------- endmodule