| EECS150 Components and Design Techniques for Digital Systems | |
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EECS150 Fall 2008 Documents |
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| Sections... |
| Top Level Verilog Files | |
| FPGA_TOP.v | Top level verilog file for the CaLinx v1 boards (Without USB) |
| FPGA_TOP2.v | Top level verilog file for the CaLinx v2 boards (With USB) |
| FPGA_TOP+.v | Top level verilog file for the CaLinx v1 boards (Without USB) with the CaLinx Expansion board |
| FPGA_TOP_CALINX2+ | Top level verilog file for the CaLinx v2 boards (With USB) with the CaLinx Expansion board |
| General Documentation | |
| [HTML] | Kramnik (Terminal Server) Instructions |
| [PDF] | IEEE Verilog Reference |
| [PDF] | Synplicity Synplify Reference |
| [PDF] | Xilinx VirtexE Datasheet |
| [PDF] | HP/Agilent 54645D Oscilloscope Tutorial |
| Textbook | |
| [HTML] | Chapter 11 |
| [HTML] | Chapter 12 |
| [HTML] | Textbook Errata |
| Tutorials | |
| [Always.pdf] | Verilog always@ block Tutorial |
| [Nets.pdf] | Verilog wire vs. reg Tutorial |
| [FSM.pdf] | Verilog "Finite State Machines" Tutorial |
| [VerilogGreenCard.pdf] | Structural Verilog Reference |
| [UsingChipScope.pdf] | ChipScope tutorial |
| [UsingSVN.pdf] | SVN tutorial |
| Review | |
| [Review 1-1] | Saturday Review Sheet #1 (Midterm 1) |
| [Review 1-1 Solutions] | Saturday Review Sheet #1 Solutions |
| [Review 1-2] | Saturday Review Sheet #2 (Midterm 1) |
| [Review 1-2 Solutions] | Saturday Review Sheet #2 Solutions |
| [Review 2-1] | Monday Review Sheet #1 (Midterm 2) |
| [Review 2-1-1 Solution] | Monday Review Sheet #1, Problem #1 Solution (Midterm 2) |
| [Review 2-1-2 Solution] | Monday Review Sheet #1, Problem #2 Solution (Midterm 2) |
| [The Whiteboard!] | The whiteboard from the review session |
| [Colorful Memories] | Final: Short design problem |
| [NoC] | Final: Long design problem |
| [The Whiteboard! (datapath from HW11)] | The whiteboard featuring the HW11 datapath |
| Project | |
| [Project Specification] | The Final Project Specification |
| [Interfaces] | The FIFO Interface that will be followed for project modules |
| [Project Extra Credit] | Extra Credit overview for the final project |
| [Example Project Report] | Example Final Project Report |
| Datasheets (CaLinx/CaLinx2) | |
| [PDF] | Schematics for the CaLinx v1 boards (Without USB) |
| [PDF] | Schematics for the CaLinx v2 boards (With USB) |
| [PDF] | Xilinx Block Select RAM+ Datasheet (XAPP130) |
| [PDF] | Micron Technologies SDRAM Chip MT48LC8M16A2TG -7E (CaLinx) |
| [PDF] | Micron Technologies SDRAM Chip MT48LC16M16A2TG -7E (CaLinx2) |
| [PDF] | Analog Devices ITU656/601 Video Encoder ADV7194 |
| [PDF] | Analog Devices ITU656/601 Video Decoder ADV7185 |
| [PDF] | Intel Quad 802.3 Ethernet Phy LXT975 |
| [PDF] | Xilinx System ACE CF Controller |
| [PDF] | National Semiconductor AC97 Audio Codec LM4549A |
| [PDF] | Phillips PDIUSBP11A USB Phy |
| Datasheets (CaLinx Expansion/CaLinx+/CaLinx2+) | |
| [PDF] | Schematics for the CaLinx Expansion boards |
| [PDF] | Hitachi/Renesas HD44780 LCD Controller Chip |
| [PDF1] [PDF2] | Lumex LCD Module |
| [PDF] | Maxim MAX3233E RS232 Driver |
| [PDF] | Chipcon RF Transceiver CC2420 802.15.4 (Zigbee) |
| [PDF] | Analog Devices ADC AD7924 (4-Channel 1MSPS 12bit Succesive Approximation) |
| [PDF] | Analog Devices 2.5V Voltage Reference REF43 |
| Protocol Documentation | |
| [PDF] | AC97 Audio Codec Standard (Revision 2.3, from Intel) |
| [PDF] | I2C Bus Specification (from Phillips) |
| [PDF] | IEEE 802.3 (Ethernet) Standard |
| [PDF] | IEEE 802.15.4 (Wireless) Standard |
| [PDF] [DOC] | N64 Game Controller Protocol |
| [PDF] [DOC] | PS2 Keyboard/Mouse Protocol |
| [PDF] [DOC] | RS232 Communication Standard |
| Video Documentation | |
| [PDF] [DOC] | Video In a Nutshell (by Tom Oberheim) |
| [PDF] [DOC] | ITU 601 Video Standard |
| [PDF] [DOC] | ITU 656 Video Standard |
| [PDF] | Charles Poynton, "A technical Introduction to Digital Video", Chapter 1 |
| Last Updated: 01/18/2009 by | |
| Chris Fletcher |