EECS150 Fall 2008 - Project Information Page

This page contains information regarding the project code, documents, and due dates. Its purpose is to track any and all revisions to each piece of material, as well as general changes to the project specification. Check back to this page regularly for updates.

General

Final Check-off Schedule

Project.pdf (Project Specification)

• Revision A (Current revision): [Posted 10/10] Initial release.

Interfaces.pdf (Interface Specification)

• Revision A (Current revision): [Posted 10/10] Initial release.

Checkpoint 1

VideoEncoder.pdf

• Revision E (Current revision): [Posted 10/15] Updated the port specification on the Video Encoder (page 8). The new port specification eliminates DataValid entirely and changes DataReady to DataRequest. See the .pdf for more information.
• Revision D: [Posted 10/13] Updated Figure 4 (Video Encoder block diagram); fixed the check-off date on the check-off page.
• Revision C: [Posted 10/10] Initial release.

Files

• Revision B: (Current revision): [Posted 10/16] Updated the VideoROM interface to match Revision E of VideoEncoder.pdf.
• Revision A: [Posted 10/12] Initial release.

TA Solution

Checkpoint 2

SDRAMController.pdf

• Revision C (Current revision): [Posted 10/19] Moved checkpoint0bb to later in the doc; changed RAMReady to InitDone; added more tips; clarified handshake.
• Revision B: [Posted 10/17] Initial release.

Files

• Revision A: [Posted 10/19] Initial release.

TA Testbench

Checkpoint 0bb Expected Values (by dipswitch SW1 and SW2)

• input 00: 00000000
• input 01: c6c042d2 (constant, no matter how many times SW1 or SW2 is pushed)
• input 10: 894..... (changes when you hit SW2)
• input 11: deafbeef

Checkpoint 3

SDRAMArbiter.pdf

• Revision B (Current revision): [Posted 10/29] Added RAMInitDone and Done signals to the input port specification of the SDRAM Arbiter. (the changes are marked in orange in the spec).
• Revision A: [Posted 10/24] Initial release.

Checkpoint3Verification.pdf (Loop-back Video)

• Revision B (Current revision): [Posted 10/29] Added ''Big Picture'' section; added port specifications for Async FIFO wrapper and the Video Decoder.
• Revision A: [Posted 10/28] Initial release.

Files

• Revision A (Current revision): [Posted 10/27] Initial release.

TA Solution

Checkpoint 4

WaveformGenerator.pdf

• Revision A (Current revision): [Posted 11/1] Initial release.

Files

• Revision B (Current revision): [Posted 11/8] Added WaveformSource.v.
• Revision A: [Posted 11/1] Initial release.

TA Solution

Checkpoint 5

AC97Audio.pdf

• Revision D (Current revision): [Posted 11/13] Fixed a typo: LM4549A.v should have been LM4549ACodec.v. There is no LM4549A.v!
• Revision C: [Posted 11/7] Initial release.

Files

• Revision A (Current revision): [Posted 11/11] Initial release.

Final Check-off

FinalCheckoff.pdf

• Revision A (Current revision): [Posted 11/17] Initial release.

TA Solution

---

Project Report

ProjectReport.pdf

• Revision A (Current revision): [Posted 11/21] Initial release.

Extra Credit

ExtraCredit.pdf

• Revision C (Current revision): [Posted 11/17] Added lab 6 audio and waveform/display coupling options (from the Final Check-off requirement). (See page 7).
• Revision B: [Posted 11/14] Added 1-pointer section; adjusted the weight of the FFT option.
• Revision A: [Posted 10/26] Initial release.