center,to,logical,flow,flowchart,DFD,DeMarco,Gane,Sarson,Yourdon,database,store,business,process
Drag onto the page, then drag the ends to center blue x
s on shapes (red indicates connection).
ates.
Resize Shape
Reposition Text
inverter,logic,digital,wiring,analog,electromechanical
Drag onto the page, then right-click to specify an alternate form.
Represents an inverter.
buffer,logic,digital,wiring,analog,electromechanical
Drag onto the page, then right-click to specify alternate form.
Represents a buffer.
clock,logic,digital,wiring,analog,electromechanical
Drag the shape onto the drawing page.
Represents a clock source.
gates,logic,digital,wiring,analog,electromechanical
Drag onto the page, then right-click to specify gate type and number of inputs and outputs.
ecified.
2
AND
1
Represents various forms of logic gates.
I/O,input,output,port,logic,digital,wiring,analog,electromechanical
Drag onto the page, then right-click to specify unidirectional or bidirectional.
Set to &Bidirectional
Unidirectional or bidirectional I/O port.
Move Inner Circle
wiring,lines,connection,electrical,layouts,Electronic,junction,paths,Transmission
Drag onto the page, then place over the junction of two lines to indicate a connection. Right-click to resize.
Resize Junction
Enable &Resizing
Place over the junction of two lines to indicate a connection. Right-click for a resizing control handle.
Determines text control handle visibility.
{D7D7DB7E-3668-43e5-AF97-97F58AB229A5}
Equipment
Equipment Description,Material,Manufacturer,Model
Hi&de Tag
E-0
Arial Unicode MS
Symbol
Wingdings
Arial
SimSun
PMingLiU
MS PGothic
Dotum
Sylfaen
Estrangelo Edessa
Vrinda
Shruti
Mangal
Tunga
Sendnya
Raavi
Dhenu
Latha
Gautami
Cordia New
MS Farsi
Gulim
Times New Roman
Courier New
Guide
TheDoc
Page-1
Gesture Format
EE Normal
Port
Named Port
Abstract IO
Module
Unit.75
Debugging / Front End
Tiny Register
Named Port Right
Software
Named Port Left
Black fill
Center Connector
Row_1
Row_2
Range
visDescription
visVersion
Logic Gate
DFD Normal
Visio 00
Bus Width
Cost
Duration
Resources
DFD Arrow End
Center to center 1
ScaleFactor
STR Connector
STR Normal
Range label
Inverter
Form
Buffer
Clock
Logic gate 2
Input
Type
SubType
Margin
LimitHeight
I/O port
Software/State
Start state
Init State
Clock Input
Inverted Input
Inverted Clock Input
Connector
Dynamic connector
TextPosition
Wire
Concrete Module
Abstract Module
Multithreaded Unit
Unit
Wrapper
Abstract Memory
Abstract I/O
Abstract Control
Abstract CPU
Abstract Network
Dynamic connector.541
Dynamic connector.542
Callout Box
Tiny FIFO
Platform
Implement
Center to center 1.57
Port/Terminal
Clock Pulse
Channel
Tiny Mux
Debug / Implement
Front End
R2 Rule
Register
FIFO
Multithreaded Implement
Junction
Label
Fast Rise
Schematic Module
Block Module
Multihtreaded Module
MT Unit
MT Implement
MT Port
MT Channel
MT Module
MT Register
Slow Rise
Data Change
Data Value
Data Tristate
Data Off
Data Uniform
Glitch
Data Glitch
Time Marker
Causality
Compiler/Tool.5
PEHideTags
TextCH
SOLSH
ShapeClass
PETagFormat
PETagNumber
PEHideTag
PEPageHideTags
PELayout
CPMSetList
PEComponentTag
Description
Material
Manufacturer
Model
Wire Gap
Compiler/Tool
Tiny Mux.58
Region
FlipFlop
Latch
Shift Register
Basic
Dependency
Clock Input.2
Dependency.14
Clock Input.3
Clock Input.4
Clock Input.5
Clock Input.6
Clock Input.7
Pull Sink
Push Source
Agnostic Pull Sink
Push Sink
Agnostic Push Sink
Pull Source
Agnostic Pull Source
Agnostic Push Source
Pull Source.10
Pull Source.8
Push Source.9
Pull Source.11
Bitfield Left
Bitfield Right
Bitfield Gap
Bitfield Value