CS 150 Homework #3
Due September 19th

(1) In a modern process, a single logic gate takes up 5 square microns. How many gates could you fit on a square chip that is 1.3 cm on a side? What if the process shrunk, so that both the leingth and width of the gate were cut in half? And why can't you actually fit this many gates onto a chip?

(2) Xilinx claims that the F and G blocks can be used for any 4 input function, and the H box can perform any 3 input function. They also claim that with the F, G, and H boxes on a clb, they can perform ANY 5 input function. Prove this.

(3) It is possible to build a 2 bit data, 1 bit control multiplexer using an inverter and 2 tri-state buffers. How do you build this? Given a 2 bit decoder and some tri states, build a multiplexer for 4 separate data lines. What changes if these lines are busses?

(4) The Mad Scientist Dr. Strazynski has created a new kind of wire, made out of a rare material called Quantium 40. This wire has the unique property that if no signal is driven on it, the wire carries a logic 0. It can be driven by tri-state buffers. However, if two tristates are connected to the same Quantium 40 wire, but are driving different values, the chip explodes. Using ONLY tri-state buffers connected to a Quantium 40 wire, design a 7 input OR gate.

(5) After reading the Xilinx documentation, why is it difficult or impossible for SpeedWave to accurately predict the timing of your design?

This page is maintained by Nick Weaver (nweaver@cs.berkeley.edu)