CS 150 Homework #9
Due Nov 7th

(1) Build a 27 bit carry lookahead adder using 3 bit wide segments. (You saw 2 bit wide segments in class, 4 bit in Katz).

(2) One astute 150 student wondered what happens if a carry select adder is built in a tree structure. Instead of having the third section of the carry select adder be normally selected, it selects from one of two larger carry select adders. Design such an adder for 64 bits. What is the performance compared to a conventional 64 bit carry select adder? What is the asymtopic behavior in time and space of such an adder when compared with a normal carry select adder and a carry lookahead adder?

(3) Your Head TA needed to build a multiplier for his 252 project. His design is now in the 150 library. Print this out and provide a written explanation for your fellow students, explaining to them how it operates. It takes 2 16 bit numbers and a start signal as input, and outputs a 32 bit number and a done signal.

(4) Design a 16 bit multiplier which takes the shortest time to multiply 2 16 bit numbers together.

(5) Open the schematic for a 4 bit adder in Xilinx (ADD4). Print it out and provide a written explanation of how it operates. How is this layed out on a Xilinx chip? How is it floorplanned? How would you change it to perform a conditional add (if a control bit is 0, the output is A, otherwise, the output is A+B) WITHOUT having it take up any additional resources on your Xilinx board? The CY components are the carry chain, and the LOC attribute determines relative location.

This page is maintained by Nick Weaver (nweaver@cs.berkeley.edu)