General Guide to Debugging

The primary tools for this search are common sense, the logic probe, the multimeter, and the oscilloscope.  The following guidlines should also help.
  1. Read the logfile output from the Xilinx Design Manager to check for suspicious warnings (see below: Reading the Logfile).
  2. Check wiring of components for proper connections.  (Important note:  Chips should never be hot.)
  3. Bad signals should be traced back to its origin.  This can be done in Xilinx by setting up debugging outputs.  Send signals to unused output pins (using OPAD's) or LED's to watch the internal values.
  4. Check the test equipment before starting to debug.  There's nothing worse than spending an hour debugging your circuit with the logic analyzer to find that the pod is broken.
  5. Since debugging is a process of elimination, tests that eliminate large portions of a circuit from considerations are the most useful.
  6. Find out what is wrong specifically and think about what might cause the incorrect output that you see.

Reading the Logfile for Errors

With Viewdraw, it's very easy to mislabel nets and pins (by misspellins, typing O for 0, etc.).  An easy first-pass check can be done by reading the log file generated by Xilinx Design Manager's compile.

Here's an example of some error messages:

WARNING:basnu - logical net "$1I48/$1I1/CLK" has no driver
WARNING:basnu - logical net "$1I6/$1I1/CEO" has no load

All components have names assigned to them by default.  These names identify a component or net all the way down to the lowest level.

In the first example above, "$1I48/$1I1/CLK" is an input pin called CLK which does not have a signal coming in.  No driver errors are usually bad because components in a design need to have all their inputs specified.  The question now is which component is it that doesn't have a clock input?  Instead of looking through all your pages of schematic, you can look at the name of the component.

From your top-level schematic, look for the component with the name $1I48.  The name of a selected component is displayed on the bottom left hand corner of the Viewdraw schematic window.  We know that it's on the first page because the name starts with a '1'.  Once you're looking at the correct page of your schematic, you can choose Edit->Select from the menu and search for the name $1I48.  (Make sure that you use the object type name for things with $'s in them.  If it's a label, that you're searching for, set the object type to label.)

Once you've found the correct component, you'll have to push into the component's schematic.  Now look for the component with the name $1I1.  When you've found it, check to make sure that there is a signal driving the CLK pin.

The deeper a component is in the design, the longer it's name will be.

The warning message, "$1I6/$1I1/CEO," says that there is an ouput pin called CEO which is not attached to anything.  This is okay because it's completely valid to ignore outputs.  However, check to make sure that you really do want to ignore that particular output.  In this example, the warning comes from a counter where the carry enable out signal has been ignored.

Instead of stopping the compilations on these warnings, Xilinx will trim away unused/unsourced components figuring that they're not important.  It's possible that your entire designed might be considered unneccessary and be trimmed away if you mislabel your clock net!

Known Software Peculiarities, and Other Errors

Finally, there are those software bugs...  The following is a list of things relating to software that we've run into so far this semester (and previous semesters).  Most of these are common--but unintuitive--mistakes.
  Well, hope that helps.  If you find another peculiar error/warning, e-mail a description of the problem and the solution to and we'll add it to this list.  Thanks!  :-)

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