#FIG 3.2 Portrait Center Inches Letter 100.00 Multiple -2 1200 2 6 375 75 9525 10575 6 825 4950 6075 5625 4 0 0 100 0 0 11 0.0000 4 150 5220 825 5100 Harvard architecture allows for Instruction prefetch ( See problem 11.4. Instruction \001 4 0 0 100 0 0 11 0.0000 4 150 2265 825 5325 prefetch is when the next instruction\001 4 0 0 100 0 0 11 0.0000 4 150 4500 825 5550 executing.) But in this problem you didn't need to worry this "pipelinig".\001 -6 6 375 1725 3750 4200 6 1875 1725 2850 2700 2 2 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 5 1914 1907 2305 1907 2305 2691 1914 2691 1914 1907 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 2 1 1 3.00 48.28 96.56 2305 2269 2789 2269 4 0 0 100 0 0 11 0.0000 4 105 375 1944 1846 MAR\001 -6 6 1875 3225 2850 4200 2 2 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 5 1914 3416 2305 3416 2305 4200 1914 4200 1914 3416 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 1 2 1 1 3.00 48.28 96.56 1 1 3.00 48.28 96.56 2305 3778 2789 3778 4 0 0 100 0 0 11 0.0000 4 105 345 1944 3355 MBR\001 -6 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 2 1 1 3.00 48.28 96.56 1099 2027 1944 2027 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 2 1 1 3.00 48.28 96.56 1099 2449 1944 2449 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 1 2 1 1 3.00 48.28 96.56 1 1 3.00 48.28 96.56 1099 3596 1944 3596 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 1 2 1 1 3.00 48.28 96.56 1099 4019 1944 4019 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 2 1 1 3.00 48.28 96.56 1159 2811 2789 2811 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 2 1 1 3.00 48.28 96.56 1159 2993 2789 2993 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 1 2 1 1 3.00 48.28 96.56 1159 3174 2789 3174 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2 672 2832 1034 2832 2 2 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 5 2789 1907 3676 1907 3676 4200 2789 4200 2789 1907 4 0 0 100 0 0 11 0.0000 4 105 195 1039 1966 PC\001 4 0 0 100 0 0 11 0.0000 4 105 165 1039 2389 IR\001 4 0 0 100 0 0 11 0.0000 4 105 870 797 3536 LD/ST DATA\001 4 0 0 100 0 0 11 0.0000 4 105 765 858 3959 Instructions\001 4 0 0 100 0 0 10 0.0000 4 105 315 797 3234 Wait\001 4 0 0 100 0 0 10 0.0000 4 105 720 375 2993 Read/Write\001 4 0 0 100 0 0 10 0.0000 4 135 495 616 2751 Request\001 4 0 0 100 0 0 11 0.0000 4 135 540 2909 3054 Memory\001 -6 6 6807 2479 7851 2740 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 2 1 1 3.00 52.28 104.57 6872 2675 7787 2675 4 0 0 100 0 0 12 0.0000 4 135 180 6807 2610 IR\001 -6 6 6825 863 7869 1125 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 2 1 1 3.00 52.28 104.57 6890 1059 7805 1059 4 0 0 100 0 0 12 0.0000 4 135 225 6825 994 PC\001 -6 6 5400 2175 8400 2325 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 1 2 1 1 3.00 52.28 104.57 6600 2250 8365 2250 4 0 0 100 0 0 11 0.0000 4 105 1050 5400 2325 Instruction Wait\001 -6 6 5250 1950 8400 2175 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 2 1 1 3.00 52.28 104.57 6622 2100 8387 2100 4 0 0 100 0 0 11 0.0000 4 150 1230 5250 2100 Instruction Request\001 -6 6 6600 1540 7841 1800 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 1 2 1 1 3.00 52.28 104.57 6862 1735 7777 1735 4 0 0 100 0 0 12 0.0000 4 135 915 6600 1670 Instructions\001 -6 6 7800 600 8400 1950 6 7800 825 8400 1275 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 2 1 1 3.00 48.28 96.56 8080 1050 8400 1050 2 2 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 5 7800 825 8100 825 8100 1275 7800 1275 7800 825 -6 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 1 2 0 0 3.00 60.00 120.00 8080 1725 8400 1725 2 2 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 5 7800 1500 8100 1500 8100 1950 7800 1950 7800 1500 4 0 0 100 0 0 11 0.0000 4 105 405 7800 1425 IMBR\001 4 0 0 100 0 0 11 0.0000 4 105 435 7800 750 IMAR\001 -6 6 5700 3900 8475 4275 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 2 1 1 3.00 52.28 104.57 6697 4079 8462 4079 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 1 2 1 1 3.00 52.28 104.57 6697 4210 8462 4210 4 0 0 100 0 0 11 0.0000 4 150 810 5718 4079 Data Request\001 4 0 0 100 0 0 11 0.0000 4 105 630 5913 4275 Data Wait\001 -6 6 7800 2625 8400 3075 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 2 1 1 3.00 48.28 96.56 8080 2850 8400 2850 2 2 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 5 7800 2625 8100 2625 8100 3075 7800 3075 7800 2625 -6 6 375 5850 4650 10532 5 1 0 1 0 7 100 0 -1 0.000 0 1 0 1 2089.389 6465.030 2327 6297 1804 6522 2274 6690 1 1 3.00 43.32 86.64 5 1 0 1 0 7 100 0 -1 0.000 0 1 0 1 2089.357 7417.453 2327 7250 1804 7473 2274 7642 1 1 3.00 43.32 86.64 5 1 0 1 0 7 100 0 -1 0.000 0 1 0 1 2088.983 8424.829 2327 8258 1804 8482 2274 8649 1 1 3.00 43.32 86.64 5 1 0 1 0 7 100 0 -1 0.000 0 1 0 1 2084.983 9592.829 2323 9426 1800 9650 2270 9817 1 1 3.00 43.32 86.64 6 2223 6187 2850 6859 1 1 0 1 0 7 100 0 -1 0.000 1 0.0000 2536 6522 295 317 2536 6522 2745 6747 4 0 0 100 0 0 11 0.0000 4 105 270 2380 6466 RES\001 -6 6 2886 6664 3429 6936 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2 2949 6723 3367 6723 4 0 0 100 0 0 11 0.0000 4 105 390 2949 6890 Reset/\001 -6 6 2682 8700 3971 8971 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2 2745 8762 3931 8762 4 0 0 100 0 0 11 0.0000 4 105 1095 2799 8932 Instruction Wait/\001 -6 6 375 9514 1664 9786 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2 438 9577 1624 9577 4 0 0 100 0 0 11 0.0000 4 105 1095 492 9746 Instruction Wait/\001 -6 1 1 0 1 0 7 100 0 -1 0.000 1 0.0000 2536 7473 295 317 2536 7473 2745 7698 1 1 0 1 0 7 100 0 -1 0.000 1 0.0000 2536 8482 295 317 2536 8482 2745 8706 1 1 0 1 0 7 100 0 -1 0.000 1 0.0000 2546 9650 295 317 2546 9650 2755 9874 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 1 4 1 1 3.00 43.32 86.64 2799 6354 3059 6187 3007 6410 3424 6187 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 2 1 1 3.00 43.32 86.64 2536 6859 2536 7138 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 2 1 1 3.00 43.32 86.64 2536 7811 2536 8146 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 2 1 1 3.00 43.32 86.64 2536 8818 2536 9378 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2 549 7194 1735 7194 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 2 1 1 3.00 43.32 86.64 2546 9972 2546 10532 4 0 0 100 0 0 11 0.0000 4 105 225 2432 7418 IF0\001 4 0 0 100 0 0 11 0.0000 4 105 225 2432 8426 IF1\001 4 0 0 100 0 0 11 0.0000 4 105 390 1282 6410 Reset/\001 4 0 0 100 0 0 11 0.0000 4 105 960 3268 6466 Reset / 0 -> PC\001 4 0 0 100 0 0 11 0.0000 4 105 1080 1962 6017 Instruction Fetch\001 4 0 0 100 0 0 11 0.0000 4 105 1095 549 7363 Instruction Wait/\001 4 0 0 100 0 0 11 0.0000 4 105 1095 2902 7811 Instruction Wait/\001 4 0 0 100 0 0 11 0.0000 4 150 1545 2902 8236 1 -> Instruction Request\001 4 0 0 100 0 0 11 0.0000 4 105 225 2411 9582 IF2\001 4 0 0 100 0 0 11 0.0000 4 105 870 2954 7071 PC -> IMAR\001 4 0 0 100 0 0 11 0.0000 4 105 855 2954 7275 PC + 1 -> PC\001 4 0 0 100 0 0 11 0.0000 4 135 1215 2902 8023 IMAR -> Memory\001 4 0 0 100 0 0 11 0.0000 4 105 1095 495 8428 Instruction Wait/\001 4 0 0 100 0 0 11 0.0000 4 150 1545 495 8876 1 -> Instruction Request\001 4 0 0 100 0 0 11 0.0000 4 135 1215 495 8653 IMAR -> Memory\001 4 0 0 100 0 0 11 0.0000 4 135 1185 2799 9143 Memory -> IMBR\001 4 0 0 100 0 0 11 0.0000 4 105 1095 2954 9989 Instruction Wait/\001 4 0 0 100 0 0 11 0.0000 4 105 810 2954 10193 IMBR -> IR\001 -6 6 5175 5850 9000 10500 5 1 0 1 0 7 100 0 -1 0.000 0 1 0 1 6814.357 7385.453 7052 7218 6529 7441 6999 7610 1 1 3.00 43.32 86.64 5 1 0 1 0 7 100 0 -1 0.000 0 1 0 1 6813.983 8392.829 7052 8226 6529 8450 6999 8617 1 1 3.00 43.32 86.64 5 1 0 1 0 7 100 0 -1 0.000 0 1 0 1 6809.983 9560.829 7048 9394 6525 9618 6995 9785 1 1 3.00 43.32 86.64 6 5700 7125 6450 7275 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2 5700 7125 6450 7125 4 0 0 100 0 0 11 0.0000 4 105 675 5724 7256 Data Wait/\001 -6 6 7500 8775 8250 8925 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2 7500 8775 8250 8775 4 0 0 100 0 0 11 0.0000 4 105 675 7524 8906 Data Wait/\001 -6 1 1 0 1 0 7 100 0 -1 0.000 1 0.0000 7261 7441 295 317 7261 7441 7470 7666 1 1 0 1 0 7 100 0 -1 0.000 1 0.0000 7271 9618 295 317 7271 9618 7480 9842 1 1 0 1 0 7 100 0 -1 0.000 1 0.0000 7261 6490 295 317 7261 6490 7470 6715 1 1 0 1 0 7 100 0 -1 0.000 1 0.0000 7261 8450 295 317 7261 8450 7470 8674 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 2 1 1 3.00 43.32 86.64 7261 6827 7261 7106 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 2 1 1 3.00 43.32 86.64 7261 7779 7261 8114 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 2 1 1 3.00 43.32 86.64 7261 8786 7261 9346 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 2 1 1 3.00 43.32 86.64 7271 9940 7271 10500 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2 8325 8175 8625 8175 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2 5850 8550 6225 8550 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2 5700 9525 6375 9525 4 0 0 100 0 0 11 0.0000 4 135 1185 7524 9111 Memory -> IMBR\001 4 0 0 100 0 0 11 0.0000 4 150 1530 6687 5985 Load Execution Sequence\001 4 0 0 100 0 0 11 0.0000 4 105 210 7125 6450 OD\001 4 0 0 100 0 0 11 0.0000 4 105 945 7650 6825 IR<15:14>=00/\001 4 0 0 100 0 0 11 0.0000 4 105 1305 7679 7039 IR<13:0> -> DMAR\001 4 0 0 100 0 0 11 0.0000 4 105 270 7125 7425 LD0\001 4 0 0 100 0 0 11 0.0000 4 105 270 7157 8394 LD1\001 4 0 0 100 0 0 11 0.0000 4 105 270 7136 9550 LD2\001 4 0 0 100 0 0 11 0.0000 4 135 1260 7650 7950 DMAR -> Memory\001 4 0 0 100 0 0 11 0.0000 4 105 675 7650 7800 Data Wait/\001 4 0 0 100 0 0 11 0.0000 4 150 1125 7650 8100 1 -> Data Request\001 4 0 0 100 0 0 11 0.0000 4 105 1035 7650 8325 1 -> Read/Write\001 4 0 0 100 0 0 11 0.0000 4 135 1260 5175 8325 DMAR -> Memory\001 4 0 0 100 0 0 11 0.0000 4 105 675 5175 8175 Data Wait/\001 4 0 0 100 0 0 11 0.0000 4 150 1125 5175 8475 1 -> Data Request\001 4 0 0 100 0 0 11 0.0000 4 105 1035 5175 8700 1 -> Read/Write\001 4 0 0 100 0 0 11 0.0000 4 105 675 5700 9675 Data Wait/\001 4 0 0 100 0 0 11 0.0000 4 105 675 7679 9957 Data Wait/\001 4 0 0 100 0 0 11 0.0000 4 105 1020 7679 10161 DMBR -> ACC\001 -6 2 2 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 5 8387 900 9525 900 9525 2400 8387 2400 8387 900 2 2 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 5 8387 2610 9525 2610 9525 4275 8387 4275 8387 2610 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 1 2 1 1 3.00 52.28 104.57 1 1 3.00 52.28 104.57 6853 3497 7650 3525 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2 6240 3753 6631 3753 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 2 1 1 3.00 52.28 104.57 6697 3882 8462 3882 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 1 2 0 0 3.00 60.00 120.00 0 0 3.00 60.00 120.00 7950 3525 8400 3525 2 2 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 5 7650 3300 7950 3300 7950 3750 7650 3750 7650 3300 4 0 0 100 0 0 16 0.0000 4 165 3000 2475 525 CS150 Homework 9 Solutions\001 4 0 0 100 0 0 11 0.0000 4 105 1635 600 1575 Princeton Architecture\001 4 0 0 100 0 0 11 0.0000 4 135 5085 450 4800 1. b. How would the state diagram in figure 11.23 change for Harvard architecture?\001 4 0 0 100 0 0 11 0.0000 4 150 2790 3150 5325 can be fetched while the present instruction is\001 4 0 0 100 0 0 11 0.0000 4 135 4995 525 1200 1. a. How would figure 11.5 change if Harvard architecture was used? (Katz 11.3)\001 4 0 0 100 0 0 15 0.0000 4 150 930 8516 1563 Instruction\001 4 0 0 100 0 0 12 0.0000 4 180 630 8647 1760 Memory\001 4 0 0 100 0 0 12 0.0000 4 180 630 8647 3263 Memory\001 4 0 0 100 0 0 15 0.0000 4 150 420 8713 3068 Data\001 4 0 0 100 0 0 12 0.0000 4 135 915 6525 3432 LD/ST Data\001 4 0 0 100 0 0 11 0.0000 4 105 1035 5521 3882 Data Read/Write\001 4 0 0 100 0 0 11 0.0000 4 105 450 7650 3225 DMBR\001 4 0 0 100 0 0 11 0.0000 4 105 480 7800 2550 DMAR\001 4 0 0 100 0 0 11 0.0000 4 105 1335 4575 1650 Harvard Architecture\001 4 0 0 100 0 0 16 0.0000 4 225 1020 6675 300 Page 1 / 4\001 -6 6 525 12000 9975 22500 5 1 0 1 0 7 100 0 -1 0.000 0 1 0 1 2699.839 14780.535 2950 14624 2411 14841 2896 15001 1 1 3.00 43.02 86.05 5 1 0 1 0 7 100 0 -1 0.000 0 1 0 1 7349.839 15005.535 7600 14849 7061 15066 7546 15226 1 1 3.00 43.02 86.05 6 3000 19650 7200 21900 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 1 2 1 1 3.00 43.63 87.27 7143 21307 3008 21307 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 1 2 1 1 3.00 43.63 87.27 7143 21122 3008 21122 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 1 2 1 1 3.00 43.63 87.27 7143 20935 3008 20935 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 1 2 1 1 3.00 43.63 87.27 7143 20749 3008 20749 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 1 2 1 1 3.00 43.63 87.27 7143 20564 3008 20564 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 1 2 1 1 3.00 43.63 87.27 7143 20378 3008 20378 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 1 2 1 1 3.00 43.63 87.27 7143 20192 3008 20192 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 1 2 1 1 3.00 43.63 87.27 7143 20006 3008 20006 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 1 2 1 1 3.00 43.63 87.27 7143 19821 3008 19821 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 1 2 1 1 3.00 43.63 87.27 7143 21496 3008 21496 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 1 2 1 1 3.00 43.63 87.27 7143 21669 3008 21669 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 1 2 1 1 3.00 43.63 87.27 7143 21842 3008 21842 4 0 0 100 0 0 11 0.0000 4 105 855 4057 19959 PC + 1 -> PC\001 4 0 0 100 0 0 11 0.0000 4 105 510 4057 19773 0 -> PC\001 4 0 0 100 0 0 11 0.0000 4 105 870 4057 20145 PC -> IMAR\001 4 0 0 100 0 0 11 0.0000 4 135 1920 4057 20331 Instruction Memory -> IMBR\001 4 0 0 100 0 0 11 0.0000 4 105 810 4057 20516 IMBR -> IR\001 4 0 0 100 0 0 11 0.0000 4 135 1950 4057 20702 IMAR -> Instruction Memory\001 4 0 0 100 0 0 11 0.0000 4 105 1305 4057 20888 IR<13:0> -> DMAR\001 4 0 0 100 0 0 11 0.0000 4 135 1575 4057 21074 DMAR -> Data Memory\001 4 0 0 100 0 0 11 0.0000 4 135 1545 4057 21260 Data Memory -> DMBR\001 4 0 0 100 0 0 11 0.0000 4 105 1020 4050 21438 DMBR -> ACC\001 4 0 0 100 0 0 11 0.0000 4 135 1545 4050 21612 DMBR -> Data Memory\001 4 0 0 100 0 0 11 0.0000 4 135 1425 4050 21785 ACC -> Data Memory\001 -6 6 3000 21900 7200 22425 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 2 1 1 3.00 49.38 98.76 7143 22354 3008 22354 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 2 1 1 3.00 49.38 98.76 7143 22113 3008 22113 4 0 0 100 0 0 11 0.0000 4 105 660 4057 22292 IR<15:14>\001 4 0 0 100 0 0 11 0.0000 4 105 525 4057 22052 AC<15>\001 -6 6 2843 12633 3487 13280 1 3 0 1 0 7 100 0 -1 0.000 1 0.0000 3163 12957 304 304 3163 12957 3379 13172 4 0 0 100 0 0 12 0.0000 4 135 270 3057 12902 OD\001 -6 6 1541 13459 2994 14113 5 1 0 1 0 7 100 0 -1 0.000 0 1 0 1 2699.825 13811.948 2950 13656 2411 13871 2896 14032 1 1 3.00 43.02 86.05 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2 1550 13602 2304 13602 4 0 0 100 0 0 12 0.0000 4 135 840 1550 13763 Data Wait/\001 -6 6 1541 15638 2994 16291 5 1 0 1 0 7 100 0 -1 0.000 0 1 0 1 2699.941 15990.965 2950 15835 2411 16049 2896 16211 1 1 3.00 43.02 86.05 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2 1550 15781 2304 15781 4 0 0 100 0 0 12 0.0000 4 135 840 1550 15942 Data Wait/\001 -6 6 7493 12858 8137 13505 1 3 0 1 0 7 100 0 -1 0.000 1 0.0000 7813 13182 304 304 7813 13182 8029 13397 4 0 0 100 0 0 12 0.0000 4 135 270 7707 13127 OD\001 -6 6 6191 13684 7644 14338 5 1 0 1 0 7 100 0 -1 0.000 0 1 0 1 7349.825 14036.948 7600 13881 7061 14096 7546 14257 1 1 3.00 43.02 86.05 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2 6200 13827 6954 13827 4 0 0 100 0 0 12 0.0000 4 135 840 6200 13988 Data Wait/\001 -6 6 6191 15863 7644 16516 5 1 0 1 0 7 100 0 -1 0.000 0 1 0 1 7349.940 16215.965 7600 16060 7061 16274 7546 16436 1 1 3.00 43.02 86.05 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2 6200 16006 6954 16006 4 0 0 100 0 0 12 0.0000 4 135 840 6200 16167 Data Wait/\001 -6 6 5325 14925 6675 15150 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2 6172 14998 6534 14998 4 0 0 100 0 0 12 0.0000 4 135 1260 5373 15144 1 -> Read/Write\001 -6 6 8250 14550 9600 14775 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2 9097 14623 9459 14623 4 0 0 100 0 0 12 0.0000 4 135 1260 8298 14769 1 -> Read/Write\001 -6 1 3 0 1 0 7 100 0 -1 0.000 1 0.0000 3163 13871 304 304 3163 13871 3379 14086 1 3 0 1 0 7 100 0 -1 0.000 1 0.0000 3163 14841 304 304 3163 14841 3379 15053 1 3 0 1 0 7 100 0 -1 0.000 1 0.0000 3163 15969 304 304 3163 15969 3379 16185 1 3 0 1 0 7 100 0 -1 0.000 1 0.0000 7813 14096 304 304 7813 14096 8029 14311 1 3 0 1 0 7 100 0 -1 0.000 1 0.0000 7813 15066 304 304 7813 15066 8029 15278 1 3 0 1 0 7 100 0 -1 0.000 1 0.0000 7813 16194 304 304 7813 16194 8029 16410 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 3 1 1 3.00 49.38 98.76 1958 18774 2391 18774 2391 19206 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 2 1 1 3.00 49.38 98.76 2637 18281 2637 19206 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 1 3 1 1 3.00 49.38 98.76 1 1 3.00 49.38 98.76 8193 19145 8193 17909 7515 17909 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 3 1 1 3.00 49.38 98.76 7946 19145 7946 18219 7515 18219 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 4 1 1 3.00 49.38 98.76 5786 18281 5786 18836 2823 18836 2823 19206 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 5 1 1 3.00 49.38 98.76 7452 19145 7452 18712 4675 18712 4675 18219 4427 18219 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 1 5 1 1 3.00 49.38 98.76 7699 19145 7699 18527 4859 18527 4859 17971 4427 17971 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 3 1 1 3.00 53.66 107.31 2992 19272 3863 19272 3863 18266 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 3 1 1 3.00 53.66 107.31 2992 19407 6076 19407 6076 18266 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2 2992 19541 6480 19541 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 2 1 1 3.00 53.66 107.31 6480 19541 6480 18266 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2 6612 19272 7015 19272 2 1 0 3 0 7 100 0 -1 0.000 0 0 -1 0 0 4 2576 17848 2576 18281 4427 18281 4427 17786 2 1 0 3 0 7 100 0 -1 0.000 0 0 -1 0 0 4 1880 19206 2992 19206 2992 22415 1880 22415 2 1 0 3 0 7 100 0 -1 0.000 0 0 -1 0 0 4 8323 19154 7150 19154 7150 22425 8323 22425 2 1 0 3 0 7 100 0 -1 0.000 0 0 -1 0 0 4 5662 17848 5662 18281 7515 18281 7515 17786 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 2 1 1 3.00 43.02 86.05 3163 13280 3163 13547 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 2 1 1 3.00 43.02 86.05 3163 14194 3163 14517 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 2 1 1 3.00 43.02 86.05 3163 15161 3163 15700 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2 3410 15180 4163 15180 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 2 1 1 3.00 43.02 86.05 3211 16251 3211 16789 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2 4372 14548 4734 14548 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2 1323 15057 1687 15057 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 2 1 1 3.00 43.02 86.05 7813 13505 7813 13772 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 2 1 1 3.00 43.02 86.05 7813 14419 7813 14742 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 2 1 1 3.00 43.02 86.05 7813 15386 7813 15925 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2 8060 15405 8813 15405 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 2 1 1 3.00 43.02 86.05 7861 16476 7861 17014 4 0 0 100 0 0 11 0.0000 4 135 4755 600 17550 1. c. How would the control signal flow change for the Harvard architecture?\001 4 0 0 100 0 0 12 0.0000 4 180 3720 750 17175 There's no change in the Branch execution cycle.\001 4 0 0 100 0 0 13 0.0000 4 150 420 6156 17971 Data\001 4 0 0 100 0 0 13 0.0000 4 150 1020 4489 17909 Instructions\001 4 0 0 100 0 0 13 0.0000 4 180 1065 7576 17848 LD/ST Data\001 4 0 0 100 0 0 13 0.0000 4 150 150 2144 19885 C\001 4 0 0 100 0 0 13 0.0000 4 150 150 2144 20120 O\001 4 0 0 100 0 0 13 0.0000 4 150 165 2144 20355 N\001 4 0 0 100 0 0 13 0.0000 4 150 135 2144 20589 T\001 4 0 0 100 0 0 13 0.0000 4 150 135 2144 20823 R\001 4 0 0 100 0 0 13 0.0000 4 150 150 2144 21058 O\001 4 0 0 100 0 0 13 0.0000 4 150 135 2144 21293 L\001 4 0 0 100 0 0 13 0.0000 4 150 150 7699 19762 D\001 4 0 0 100 0 0 13 0.0000 4 150 165 7699 19997 A\001 4 0 0 100 0 0 13 0.0000 4 150 135 7699 20231 T\001 4 0 0 100 0 0 13 0.0000 4 150 165 7699 20466 A\001 4 0 0 100 0 0 13 0.0000 4 150 120 7699 20700 P\001 4 0 0 100 0 0 13 0.0000 4 150 165 7699 20934 A\001 4 0 0 100 0 0 13 0.0000 4 150 135 7699 21170 T\001 4 0 0 100 0 0 13 0.0000 4 150 150 7699 21403 H\001 4 0 0 100 0 0 13 0.0000 4 150 930 3008 17971 Instruction\001 4 0 0 100 0 0 13 0.0000 4 195 750 3008 18206 Memory\001 4 0 0 100 0 0 13 0.0000 4 195 750 6156 18144 Memory\001 4 0 0 100 0 0 13 0.0000 4 150 495 1835 18960 Reset\001 4 0 0 100 0 0 13 0.0000 4 150 930 1650 18342 Instruction\001 4 0 0 100 0 0 13 0.0000 4 150 405 2144 18527 Wait\001 4 0 0 100 0 0 13 0.0000 4 150 210 7576 18157 IR\001 4 0 0 100 0 0 13 0.0000 4 150 420 2885 18774 Data\001 4 0 0 100 0 0 13 0.0000 4 150 405 3316 18774 Wait\001 4 0 0 100 0 0 13 0.0000 4 150 270 4489 18157 PC\001 4 0 0 100 0 0 13 0.0000 4 195 1680 3125 19205 Instruction Request\001 4 0 0 100 0 0 13 0.0000 4 195 1170 4803 19340 Data Request\001 4 0 0 100 0 0 13 0.0000 4 180 990 6143 19474 Read/Write\001 4 0 0 100 0 0 16 0.0000 4 225 4290 4275 12225 CS150 Homework 9 Solutions ( Page 2 / 4 )\001 4 0 0 100 0 0 12 0.0000 4 180 1995 1994 12417 Store Execution Sequence\001 4 0 0 100 0 0 12 0.0000 4 135 300 3057 13816 ST0\001 4 0 0 100 0 0 12 0.0000 4 135 300 3057 14785 ST1\001 4 0 0 100 0 0 12 0.0000 4 135 840 3410 15341 Data Wait/\001 4 0 0 100 0 0 12 0.0000 4 180 1440 3410 15545 0 -> Data Request\001 4 0 0 100 0 0 12 0.0000 4 135 1215 3501 13169 IR<15:14> = 01/\001 4 0 0 100 0 0 12 0.0000 4 135 1560 3501 13387 IR<13:0> -> DMAR\001 4 0 0 100 0 0 12 0.0000 4 135 1095 3501 13605 AC -> DMBR\001 4 0 0 100 0 0 12 0.0000 4 135 300 3002 15916 ST2\001 4 0 0 100 0 0 12 0.0000 4 135 840 3573 14041 Data Wait/\001 4 0 0 100 0 0 12 0.0000 4 180 1440 3573 14477 1 -> Data Request\001 4 0 0 100 0 0 12 0.0000 4 135 1260 3573 14694 0 -> Read/Write\001 4 0 0 100 0 0 12 0.0000 4 135 840 3356 16509 Data Wait/\001 4 0 0 100 0 0 12 0.0000 4 135 840 525 14548 Data Wait/\001 4 0 0 100 0 0 12 0.0000 4 180 1440 525 14984 1 -> Data Request\001 4 0 0 100 0 0 12 0.0000 4 135 1260 525 15202 0 -> Read/Write\001 4 0 0 100 0 0 11 0.0000 4 135 1575 525 14694 DMAR -> Data Memory\001 4 0 0 100 0 0 11 0.0000 4 135 1545 525 14840 DMBR -> Data Memory\001 4 0 0 100 0 0 11 0.0000 4 135 1575 3573 14185 DMAR -> Data Memory\001 4 0 0 100 0 0 11 0.0000 4 135 1545 3573 14331 DMBR -> Data Memory\001 4 0 0 100 0 0 12 0.0000 4 135 840 8060 15566 Data Wait/\001 4 0 0 100 0 0 12 0.0000 4 135 1560 8151 13612 IR<13:0> -> DMAR\001 4 0 0 100 0 0 12 0.0000 4 135 840 8006 16734 Data Wait/\001 4 0 0 100 0 0 12 0.0000 4 180 1905 6644 12642 Add Execution Sequence\001 4 0 0 100 0 0 12 0.0000 4 135 1215 8151 13394 IR<15:14> = 10/\001 4 0 0 100 0 0 12 0.0000 4 135 840 5298 14641 Data Wait/\001 4 0 0 100 0 0 12 0.0000 4 180 1440 5400 14925 1 -> Data Request\001 4 0 0 100 0 0 12 0.0000 4 135 840 8223 14266 Data Wait/\001 4 0 0 100 0 0 12 0.0000 4 180 1440 8250 14550 1 -> Data Request\001 4 0 0 100 0 0 12 0.0000 4 180 1890 8060 15770 Data Memory -> DMBR\001 4 0 0 100 0 0 12 0.0000 4 135 1785 8025 16950 DMBR + ACC -> ACC\001 4 0 0 100 0 0 12 0.0000 4 135 360 7707 14041 AD0\001 4 0 0 100 0 0 12 0.0000 4 135 360 7707 15010 AD1\001 4 0 0 100 0 0 12 0.0000 4 135 360 7652 16141 AD2\001 4 0 0 100 0 0 11 0.0000 4 135 1575 8223 14410 DMAR -> Data Memory\001 4 0 0 100 0 0 11 0.0000 4 135 1575 5298 14785 DMAR -> Data Memory\001 -6 6 975 24000 10050 34125 6 975 24000 10050 34125 6 8187 26758 8893 29513 6 8187 26758 8893 29513 2 2 1 1 0 7 100 0 -1 4.000 0 0 -1 0 0 5 8257 28524 8893 28524 8893 29513 8257 29513 8257 28524 2 2 1 1 0 7 100 0 -1 4.000 0 0 -1 0 0 5 8187 26758 8823 26758 8823 27747 8187 27747 8187 26758 -6 4 0 0 100 0 0 11 0.0000 4 105 345 8399 29018 MBR\001 4 0 0 100 0 0 11 0.0000 4 105 375 8328 27252 MAR\001 -6 6 1050 28383 1615 29230 2 2 1 1 0 7 100 0 -1 4.000 0 0 -1 0 0 5 1094 28418 1615 28418 1615 29230 1094 29230 1094 28418 4 0 0 100 0 0 9 0.0000 4 75 135 1210 28824 IR\001 -6 6 5250 26925 5550 27150 2 1 0 1 0 7 100 0 20 0.000 0 0 -1 0 0 4 5475 26925 5400 27150 5550 27150 5475 26925 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2 5400 27075 5250 27075 -6 6 975 30075 9150 34125 6 975 30075 9150 31200 4 0 0 100 0 0 12 0.0000 4 135 405 975 30225 ADD\001 4 0 0 100 0 0 12 0.0000 4 135 5385 1875 30225 ACC + Rx1x0 -> ACC Rx1x0 -> BUS TRx1x0\001 4 0 0 100 0 0 12 0.0000 4 180 7170 1875 30450 ( Bus Always goes to ALU so no instruction necessary to get BUS to ALU)\001 4 0 0 100 0 0 12 0.0000 4 180 7260 1875 30675 ( ACC Always goes to ALU so no instruction necessary to get ACC to ALU)\001 4 0 0 100 0 0 12 0.0000 4 135 5220 1875 30900 ACC + BUS -> ALUOUT ADD\001 4 0 0 100 0 0 12 0.0000 4 180 6435 1875 31125 ALUOUT -> ACC SELSRC = 0, AC_LD\001 -6 6 975 31200 9150 32325 4 0 0 100 0 0 12 0.0000 4 180 7170 1875 31575 ( Bus Always goes to ALU so no instruction necessary to get BUS to ALU)\001 4 0 0 100 0 0 12 0.0000 4 180 7260 1875 31800 ( ACC Always goes to ALU so no instruction necessary to get ACC to ALU)\001 4 0 0 100 0 0 12 0.0000 4 135 405 975 31350 AND\001 4 0 0 100 0 0 12 0.0000 4 135 5370 1875 31350 ACC AND Rx1x0 -> ACC Rx1x0 -> BUS TRx1x0\001 4 0 0 100 0 0 12 0.0000 4 135 5610 1875 32025 ACC AND BUS -> ALUOUT AND\001 4 0 0 100 0 0 12 0.0000 4 180 6435 1875 32250 ALUOUT -> ACC SELSRC = 0, AC_LD\001 -6 6 975 32325 9150 33000 4 0 0 100 0 0 12 0.0000 4 135 525 975 32475 COMP\001 4 0 0 100 0 0 12 0.0000 4 135 1920 1875 32475 ~ACC -> ACC \001 4 0 0 100 0 0 12 0.0000 4 180 5955 3150 32475 ( ACC Always goes to ALU so no instruction necessary to get ACC to ALU)\001 4 0 0 100 0 0 12 0.0000 4 135 5475 1875 32700 ~ACC -> ALUOUT COMPA\001 4 0 0 100 0 0 12 0.0000 4 180 6435 1875 32925 ALUOUT -> ACC SELSRC = 0, AC_LD\001 -6 6 975 33000 9150 33675 4 0 0 100 0 0 12 0.0000 4 180 5955 3150 33150 ( ACC Always goes to ALU so no instruction necessary to get ACC to ALU)\001 4 0 0 100 0 0 12 0.0000 4 135 315 975 33150 INC\001 4 0 0 100 0 0 12 0.0000 4 135 2100 1875 33150 ACC + 1 -> ACC \001 4 0 0 100 0 0 12 0.0000 4 135 5130 1875 33375 ACC + 1 -> ALUOUT INC\001 4 0 0 100 0 0 12 0.0000 4 180 6435 1875 33600 ALUOUT -> ACC SELSRC = 0, AC_LD\001 -6 6 975 33675 7050 34125 4 0 0 100 0 0 12 0.0000 4 180 5145 1875 33825 RSR(R1) -> R1 RSR RSR\001 4 0 0 100 0 0 12 0.0000 4 180 5145 1875 34050 ASR(R1) -> R1 ASR ASR\001 4 0 0 100 0 0 12 0.0000 4 135 345 975 33825 RSR\001 4 0 0 100 0 0 12 0.0000 4 135 360 975 34050 ASR\001 -6 -6 6 6825 27075 7425 27825 4 0 0 100 0 0 11 0.0000 4 105 330 6853 27186 ADD\001 4 0 0 100 0 0 11 0.0000 4 105 345 6853 27398 AND\001 4 0 0 100 0 0 11 0.0000 4 105 285 6853 27610 INC\001 4 0 0 100 0 0 11 0.0000 4 105 570 6853 27822 COMPA\001 -6 2 2 1 1 0 7 100 0 -1 4.000 0 0 -1 0 0 5 8964 27535 9600 27535 9600 28524 8964 28524 8964 27535 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2 3170 27323 3170 28948 2 2 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 5 5290 27323 5714 27323 5714 28948 5290 28948 5290 27323 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 2 1 1 2.00 56.52 113.05 3311 27323 3311 26758 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 2 1 1 2.00 56.52 113.05 3029 27323 3029 26758 2 1 1 1 0 7 100 0 -1 4.000 0 0 -1 1 0 2 1 1 2.00 56.52 113.05 3029 29513 3029 28948 2 1 1 1 0 7 100 0 -1 4.000 0 0 -1 1 0 2 1 1 2.00 56.52 113.05 3311 29513 3311 28948 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 3 1 1 2.00 56.52 113.05 6067 26758 6067 27464 6350 27464 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 8 6350 27323 6350 27817 6632 28171 6350 28524 6350 28948 6915 28241 6915 27959 6350 27323 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2 6915 28100 7268 28100 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2 6632 27676 6632 27252 2 1 1 1 0 7 100 0 -1 4.000 0 0 -1 1 0 2 1 1 2.00 56.52 113.05 7692 27040 8187 27040 2 1 1 1 0 7 100 0 -1 4.000 0 0 -1 1 0 3 1 1 2.00 56.52 113.05 8823 27040 9247 27040 9247 27535 2 1 1 1 0 7 100 0 -1 4.000 0 0 -1 1 1 3 1 1 2.00 56.52 113.05 1 1 2.00 56.52 113.05 9247 28524 9247 29018 8893 29018 2 1 1 1 0 7 100 0 -1 4.000 0 0 -1 1 1 2 1 1 2.00 56.52 113.05 1 1 2.00 56.52 113.05 7692 28806 8257 28806 2 1 1 1 0 7 100 0 -1 4.000 0 0 -1 1 1 2 1 1 2.00 56.52 113.05 1 1 2.00 56.52 113.05 1615 27323 2251 27323 2 1 1 1 0 7 100 0 -1 4.000 0 0 -1 1 1 2 1 1 2.00 56.52 113.05 1 1 2.00 56.52 113.05 1615 28736 2251 28736 2 2 1 1 0 7 100 0 -1 4.000 0 0 -1 0 0 5 1107 26970 1628 26970 1628 27782 1107 27782 1107 26970 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2 5325 28425 5025 28425 2 1 0 1 0 7 100 0 20 0.000 0 0 -1 0 0 4 3300 27000 3225 27225 3375 27225 3300 27000 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2 3600 27150 3375 27150 2 2 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 5 2251 26758 7669 26758 7669 29513 2251 29513 2251 26758 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2 4350 27750 4575 27750 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2 4350 28125 4575 28125 2 2 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 5 3912 27323 4336 27323 4336 28948 3912 28948 3912 27323 2 1 1 1 0 7 100 0 -1 4.000 0 0 -1 1 0 2 1 1 2.00 56.52 113.05 4124 29513 4124 28948 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 2 0 0 3.00 60.00 120.00 4124 27323 4124 26758 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 2 0 0 3.00 60.00 120.00 5502 27323 5502 26758 2 1 0 1 0 7 100 0 20 0.000 0 0 -1 0 0 4 4125 27000 4050 27225 4200 27225 4125 27000 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2 4425 27150 4200 27150 2 2 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 5 2775 27300 3525 27300 3525 28950 2775 28950 2775 27300 2 1 0 1 0 7 100 0 20 0.000 0 0 -1 0 0 4 3000 27000 2925 27225 3075 27225 3000 27000 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2 3000 27150 2775 27150 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 5 5850 28950 5850 29325 6000 29400 6000 28875 5850 28950 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 3 0 0 3.00 60.00 120.00 5850 29250 5475 29250 5475 28950 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 3 0 0 3.00 60.00 120.00 7275 28125 7275 29025 6000 29025 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 3 0 0 3.00 60.00 120.00 7275 29550 7275 29250 6000 29250 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2 5925 29400 5175 29400 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 4 0 0 3.00 60.00 120.00 5550 27225 5850 27225 5850 28725 6300 28725 4 0 0 100 0 0 12 0.0000 4 180 6150 1275 29775 2. b. RTN and micro-operations for single bus datapath for specified instructions.\001 4 0 0 100 0 0 11 0.0000 4 105 390 9105 28100 MEM\001 4 0 0 100 0 0 11 0.0000 4 105 180 5360 27676 R0\001 4 0 0 100 0 0 11 0.0000 4 105 330 5360 28100 ACC\001 4 0 0 100 0 0 9 0.0000 4 75 165 1222 27376 PC\001 4 0 0 100 0 0 16 0.0000 4 225 4290 5700 24225 CS150 Homework 9 Solutions ( Page 3 / 4 )\001 4 0 0 100 0 0 11 0.0000 4 105 270 2475 27075 TR3\001 4 0 0 100 0 0 11 0.0000 4 105 270 3525 27075 TR2\001 4 0 0 100 0 0 11 0.0000 4 105 285 4500 27675 RSR\001 4 0 0 100 0 0 11 0.0000 4 105 300 4500 28050 ASR\001 4 0 0 100 0 0 11 0.0000 4 105 180 3240 27605 R2\001 4 0 0 100 0 0 11 0.0000 4 105 180 2850 27600 R3\001 4 0 0 100 0 0 11 0.0000 4 105 240 3975 28050 Rot\001 4 0 0 100 0 0 11 0.0000 4 105 180 3983 27676 R1\001 4 0 0 100 0 0 11 0.0000 4 105 270 4350 27075 TR1\001 4 0 0 100 0 0 11 0.0000 4 105 270 5025 27075 TR0\001 4 0 0 100 0 0 12 0.0000 4 165 1965 1125 24150 2. Katz Ch. 11, Problem 7.\001 4 0 0 100 0 0 12 0.0000 4 180 2235 1275 24450 a. Design single bus datapath\001 4 0 0 100 0 0 12 0.0000 4 180 1650 1425 24750 Datapath information:\001 4 0 0 100 0 0 12 0.0000 4 180 990 1425 24975 Components:\001 4 0 0 100 0 0 12 0.0000 4 165 3255 1350 25650 COMP, INC, RSR, ASR, ADD, AND\001 4 0 0 100 0 0 12 0.0000 4 135 960 1425 25425 Instructions:\001 4 0 0 100 0 0 12 0.0000 4 180 1170 1425 25875 Datapath style:\001 4 0 0 100 0 0 12 0.0000 4 180 1140 1425 26100 Single bus\001 4 0 0 100 0 0 12 0.0000 4 180 7050 1500 25200 Single accumulator ( R0 ), rotating shifter ( R1 ), two general purpose registers ( R3, R2 )\001 4 0 0 100 0 0 12 0.0000 4 180 4440 4875 25425 ( R1 & R0 can also be used as general purpose registers. )\001 4 0 0 100 0 0 11 0.0000 4 150 495 4725 28350 AC_LD\001 4 0 0 100 0 0 12 0.0000 4 135 135 6375 28650 A\001 4 0 0 100 0 0 12 0.0000 4 135 120 6375 27750 B\001 4 0 0 100 0 0 12 0.0000 4 135 675 4500 29325 SELSRC\001 4 0 0 100 0 0 8 0.0000 4 75 60 5925 29100 0\001 4 0 0 100 0 0 8 0.0000 4 75 60 5925 29325 1\001 4 0 0 100 0 0 11 0.0000 4 105 285 6975 26625 BUS\001 4 0 0 100 0 0 12 0.0000 4 180 5295 1875 30000 RTN Micro-instructions Signals\001 4 0 0 100 0 0 12 0.0000 4 180 8325 1425 26325 Other components that aren't used in this problem are drawn in in dotted lines. Tristate buffers are all BUFEs.\001 4 0 0 100 0 0 12 0.0000 4 135 240 7275 30225 = 1\001 4 0 0 100 0 0 12 0.0000 4 135 240 7275 31350 = 1\001 4 0 0 100 0 0 12 0.0000 4 180 690 6150 27150 ALU Op:\001 -6 -6 6 450 36000 9675 46050 5 1 0 1 0 7 100 0 -1 0.000 0 1 0 1 6125.000 37906.000 6525 38325 6675 37725 6600 37575 0 0 3.00 60.00 120.00 5 1 0 1 0 7 100 0 -1 0.000 0 1 0 1 1250.000 37906.000 1650 38325 1800 37725 1725 37575 0 0 3.00 60.00 120.00 6 1256 45770 9090 46050 6 1256 45770 9090 46050 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 4 9090 46050 7422 46050 7203 45770 1256 45770 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 4 9017 45770 7422 45770 7203 46050 1256 46050 -6 -6 6 1275 40350 9225 40575 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 11 1323 40560 2701 40560 2701 40350 4442 40350 4442 40560 6110 40560 6110 40350 7924 40350 7924 40518 7924 40560 9158 40560 -6 6 1350 41250 9300 41475 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 6 1350 41475 2874 41475 2874 41265 6282 41265 6282 41475 9257 41475 -6 6 1275 41775 9150 42000 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 6 1275 41888 3132 41888 3281 41775 6847 41775 7070 41888 9150 41888 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 4 3132 41888 3281 42000 6847 42000 7070 41888 -6 6 1275 42300 9225 42525 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 3 1275 42300 3525 42300 3750 42525 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 3 1275 42525 3525 42525 3750 42300 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 4 3750 42525 7275 42525 7500 42300 9225 42300 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 4 3750 42300 7275 42300 7500 42525 9225 42525 -6 6 1275 40875 9225 41100 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 3 9225 40875 6975 40875 6750 41100 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 3 9225 41100 6975 41100 6750 40875 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 4 6750 41100 3225 41100 3000 40875 1275 40875 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 4 6750 40875 3225 40875 3000 41100 1275 41100 -6 6 1350 42825 9300 43050 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 6 1350 43050 2873 43050 2873 42840 6283 42840 6283 43050 9257 43050 -6 6 600 43370 9015 43650 6 1181 43370 9015 43650 6 1181 43370 9015 43650 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 4 9015 43650 7347 43650 7128 43370 1181 43370 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 4 8942 43370 7347 43370 7128 43650 1181 43650 -6 -6 4 0 0 100 0 0 12 0.0000 4 135 375 600 43650 ACC\001 -6 1 3 0 1 0 7 100 0 -1 0.000 1 0.0000 6225 37350 375 375 6225 37350 6450 37650 1 3 0 1 0 7 100 0 -1 0.000 1 0.0000 6225 38550 375 375 6225 38550 6450 38850 1 3 0 1 0 7 100 0 -1 0.000 1 0.0000 1350 37350 375 375 1350 37350 1575 37650 1 3 0 1 0 7 100 0 -1 0.000 1 0.0000 1350 38550 375 375 1350 38550 1575 38850 1 1 0 1 0 7 100 0 -1 0.000 1 0.0000 6223 45295 72 70 6223 45295 6295 45295 1 1 0 1 0 7 100 0 -1 0.000 1 0.0000 6111 40486 72 70 6111 40486 6184 40486 1 1 0 1 0 7 100 0 -1 0.000 1 0.0000 2850 41400 72 70 2850 41400 2922 41400 1 1 0 1 0 7 100 0 -1 0.000 1 0.0000 6300 42975 72 70 6300 42975 6373 42975 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 11 1247 44975 2625 44975 2625 44625 4366 44625 4366 44975 6034 44975 6034 44625 7848 44625 7848 44905 7848 44975 9082 44975 2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 6 1275 45450 2798 45450 2798 45170 6208 45170 6208 45450 9182 45450 3 2 0 1 0 7 100 0 -1 0.000 0 1 0 3 0 0 3.00 57.05 114.10 6242 45310 6750 45450 7275 45750 0.000 -1.000 0.000 3 2 0 1 0 7 100 0 -1 0.000 0 1 0 3 0 0 3.00 57.05 114.10 2855 41420 3000 41700 3075 41850 0.000 -1.000 0.000 3 2 0 1 0 7 100 0 -1 0.000 0 1 0 4 0 0 3.00 57.05 114.10 3075 41925 3150 42225 3225 42225 3525 42450 0.000 -1.000 -1.000 0.000 3 2 0 1 0 7 100 0 -1 0.000 0 1 0 4 0 0 3.00 57.05 114.10 6225 40500 7058 41620 6769 42671 7203 43372 0.000 -1.000 -1.000 0.000 3 2 0 1 0 7 100 0 -1 0.000 0 1 0 3 0 0 3.00 57.05 114.10 6330 43009 6675 43425 7128 43500 0.000 -1.000 0.000 4 0 0 100 0 0 12 0.0000 4 180 1830 900 36750 Draw the state diagram.\001 4 0 0 100 0 0 11 0.0000 4 105 3015 600 36525 2. c. Consider execution of the ADD instruction. \001 4 0 0 100 0 0 12 0.0000 4 180 1830 5925 36750 Draw the state diagram.\001 4 0 0 100 0 0 12 0.0000 4 135 270 6075 37350 OD\001 4 0 0 100 0 0 12 0.0000 4 135 345 6075 38550 RES\001 4 0 0 100 0 0 12 0.0000 4 135 1470 6900 37575 Instruction = 1010 /\001 4 0 0 100 0 0 12 0.0000 4 135 345 6900 37800 RSR\001 4 0 0 100 0 0 12 0.0000 4 135 1380 5700 39375 It takes one state.\001 4 0 0 100 0 0 11 0.0000 4 105 2985 5625 36525 2. d. Consider execution of the RSR instruction. \001 4 0 0 100 0 0 12 0.0000 4 180 3540 450 40125 3. a. Draw timing diagram for ADD instruction.\001 4 0 0 100 0 0 12 0.0000 4 135 270 1200 37350 OD\001 4 0 0 100 0 0 12 0.0000 4 135 1095 2025 37575 OPCode = 00 /\001 4 0 0 100 0 0 12 0.0000 4 135 345 1200 38550 RES\001 4 0 0 100 0 0 12 0.0000 4 180 1965 825 39600 registers as data sources.\001 4 0 0 100 0 0 12 0.0000 4 135 2565 825 39375 It takes one state when done with\001 4 0 0 100 0 0 12 0.0000 4 180 3435 525 44400 b. Draw timing diagram for RSR instruction.\001 4 0 0 100 0 0 12 0.0000 4 135 360 675 45000 CLK\001 4 0 0 100 0 0 12 0.0000 4 135 345 675 45450 RSR\001 4 0 0 100 0 0 12 0.0000 4 135 210 675 46050 R1\001 4 0 0 100 0 0 12 0.0000 4 180 1785 3000 45975 RSR ( Previous Value )\001 4 0 0 100 0 0 12 0.0000 4 180 1485 7500 45975 RSR ( New Value )\001 4 0 0 100 0 0 16 0.0000 4 225 4290 5325 36225 CS150 Homework 9 Solutions ( Page 4 / 4 )\001 4 0 0 100 0 0 12 0.0000 4 180 2970 2025 38025 ALU -> ACC ( AC_LD, SELSRC = 0 )\001 4 0 0 100 0 0 12 0.0000 4 180 2415 2025 37800 R[x1x0] -> BUS ( TRx1x0 = 1 )\001 4 0 0 100 0 0 12 0.0000 4 135 360 675 40575 CLK\001 4 0 0 100 0 0 12 0.0000 4 135 75 1950 42525 ?\001 4 0 0 100 0 0 12 0.0000 4 135 1050 4575 42525 ACC + Rx1x0\001 4 0 0 100 0 0 12 0.0000 4 135 75 8250 42525 ?\001 4 0 0 100 0 0 12 0.0000 4 135 585 525 41475 TRx1x0\001 4 0 0 100 0 0 12 0.0000 4 135 360 675 41925 BUS\001 4 0 0 100 0 0 12 0.0000 4 135 675 1650 41850 Hi-Z\001 4 0 0 100 0 0 12 0.0000 4 135 675 7575 41850 Hi-Z\001 4 0 0 100 0 0 12 0.0000 4 135 480 4725 42000 Rx1x0\001 4 0 0 100 0 0 12 0.0000 4 135 375 675 42375 ALU\001 4 0 0 100 0 0 12 0.0000 4 135 75 1950 41100 ?\001 4 0 0 100 0 0 12 0.0000 4 135 405 4650 41100 ADD\001 4 0 0 100 0 0 12 0.0000 4 180 585 525 42975 AC_LD\001 4 0 0 100 0 0 12 0.0000 4 135 75 8175 41100 ?\001 4 0 0 100 0 0 12 0.0000 4 180 1350 2025 38250 ADD -> ALU Op\001 4 0 0 100 0 0 12 0.0000 4 180 1815 2775 43575 ACC ( Previous Value )\001 4 0 0 100 0 0 12 0.0000 4 180 1515 7425 43575 ACC ( New Value )\001 4 0 0 100 0 0 12 0.0000 4 180 645 525 41100 ALU Op\001 -6