Synchronous Design Rules

1. Use only one clock in your design, (using CLOCK and CLOCK* is fine). If you need a slower signal, such as for the serial output, use clock enables rather than a separate slower clock.
2. All inputs to your design must be synchronized, including VSYNC, CSYNC, Spare button, etc.
3. Never gate the clock, use clock enables instead.
4. Avoid clock skew, use BUFGS to globally distribute your single clock throughout the Xilinx part.
5. The only safe asynchronous control signal is the Global Set/Reset using the STARTUP block. (This signal should be driven by an appropriate RC filtered switch to ensure adequate RESET pulse width).
6. Never build your own latches in Xilinx. Coupled Mealey machines create undesirable feedback paths through the output decoders during any state transition. Even if the output is not supposed to change during a state transition, remember that the output decoders are just look up tables, and will glitch when address lines change. Synchronous Mealey machines and Moore machines are fine.
7. The minimum period for a FSM is . Use the Timing Analyzer in the Xilinx Design Manager to verify that your worst case net routing of the compiled design is less than your smallest clock period. (Note that the delay changes everytime you recompile your design, since the compilation uses non-deterministic algorithms).