Name: _______________________________________ Name: _______________________________________
Lab Section: 

6 Checkoffs

6.1 Prelab questions (refer to TA schematic)
1. What is ENTER connected to (include direct and indirect sources)? Why? 
 
2. What do you expect to see when the lock is opened? 
 
3. Where does the clock signal come from and where is it output (which LED)? 
 
4. Why are CODE0 and CODE1 not debounced? 
 
 
 
6.2 Questions
 

1. In terms of buttons, switch settings, and lights illumination, give instructions for opening the lock. 
2. Explain the three wire-wrap wires on the board. Why are they there? Why does SW4-7 have to be closed? 
 
3. By looking at the report files, how many CLBs does your design use? 
 
 
    1. Working Xilinx Lock
    TA:
    ___________________ (40%)
    2. Questions answered
    TA:
    ___________________ (20%)
    3. Debugger waveforms
    TA:
    ___________________ (40%)
    Turned in on time
    TA:
    ___________________ (x100%)
    Turned in 1 wk late
    TA:
    ___________________ (x50%)