4. EXAMPLE: FSM DESIGN
4.1 Design a Mealey machine that can detect any sequence of “1 followed by 1 followed by 0” on input Z. Output SEQ.DET.H should be asserted as soon as any 1,1,0 is detected for ~1 clock. Input data changes after ? of clock.
4.2 Make up data 0,1,0,1,1,1,0,0,1