//////////////////////////////////////////////////////////
// LAB 4 - HDL FPGA Toolflow
//
// Top level file used for synthesis.  
//
// By: Yatish Patel and Norm Zhou
// Date: Feb-14-2002
//
// Do not modify this file!
//
module top_synth (clk_pin, rst_pin, in_pin, out_pin) ;

input clk_pin;
input rst_pin ; 
input [7:0] in_pin; 
output [7:0] out_pin ;
wire clk,rst;
wire [7:0] out;

// The reset from the board is asserted low so lets invert
// it to make it asserted high.
assign rst = ~ rst_pin;

// Same with the output LEDs
assign out_pin = ~out;

// Assign our reset pin to the Xilinx global reset net.
STARTUP startup_block (.GSR(rst)); 

assign clk = clk_pin;

// Instantiate the module and pass in all the signals
top top(.clk(clk),.rst(rst),.in(in_pin),.out(out));

endmodule