//////////////////////////////////////////////////////////
// LAB 4 - HDL FPGA Toolflow
//
// Top level file used for synthesis.  
//
// By: Yatish Patel and Norm Zhou
// Date: Feb-14-2002
//
module top_tb;

   wire [7:0] out;
   reg [7:0]  in;
   reg 	      clk;
   reg 	      rst;
   
   top t(clk,rst,in,out);

   always
     begin
	#10 clk = ~clk; // this adds asserts the clk wire to alternate
	                // every 10 simulation time steps  
     end
   
   initial
     begin
	clk= 1'b0; //initializes the clk to zero at beginning of simulation

	//Reset the circuit here
	
	#40; //advancese the simulation 40 time steps.


	$finish;
     end // initial begin
   

endmodule // top_tb