EECS150 Components and Design Techniques for Digital Systems | |
EECS150 Spring 2004 |
|
Home | Calendar | Grades | Documents | Staff | Syllabus | Schedule | Old Websites | Links |
Course Administration |
No Homework |
Lec #1: Instrumentation [PDF] [] |
||
Transistor and Gate Logic [PDF]
[] |
||||
Combinational Logic [PDF]
[] |
Lab #1: Instrumentation [ZIP] Lec #2: Cad Tool Flow [PDF] [] |
|||
Programmable Logic: PAL/PLA and FPGA [PDF]
[] |
||||
Verilog Hardware Description Language [PDF]
[] |
Lab #2: Cad Tool Flow [ZIP] Lec #3: Verilog Simulation [PDF] [] |
|||
Basic Finite State Machines: Flip-Flops,
Registers, Shifters, Counters [PDF] [] |
||||
Moore and Mealy Machines [PDF]
[] |
Lab #3: Verilog Simulation [ZIP] Lec #4: Verilog Synthesis [PDF] [] |
|||
FSM Synthesis, State Machine Timing [PDF]
[] |
||||
Midterm I Review [PDF] [] (Review in the lab, 125Cory @ 6-8pm) |
No Homework |
Lab #4: Verilog Synthesis [ZIP] Lec #5: Debugging [PDF] [] |
||
Midterm I (Info: [PDF], Solution: [ZIP], Grade Distribution: [PDF]) |
||||
6 |
24 Feb |
Case Study: SDRAM/Memory Controller [PDF]
[] |
Lab #5: Debugging [ZIP] Lec #6: SDRAM Controller, I [PDF] [] |
|
26 Feb |
Project Description: Multimedia Network Router
[PDF] [] |
|||
Datapath Building Blocks: Arithmetic Units,
Register Files, Shifters, FIFOs, Memories [PDF]
[] |
Ckpt #1: SDRAM Controller (2 weeks) [ZIP] Lec #7: SDRAM Controller, II [PDF] [] |
|||
Datapath Interconnection: Point-to-Point,
Single Bus, Mixed Strategy [PDF] [] |
||||
Datapath Control: State Machines for Control;
Register Transfer Abstraction [PDF] [] |
Ckpt #1: SDRAM Controller (Due) Lec #8: AC97 Control & Audio [PDF] [] |
|||
Datapath Control: Microprogramming [PDF]
[] |
||||
Control Timing, Pipelining, Re-timing [] |
Ckpt #2: AC97 Controller (2 weeks) [ZIP] Lec #9: Tips and Techniques [PDF] [] |
|||
Enjoy Yourselves |
||||
Midterm II Review [PDF] [] (in the lab 125Cory @ 4-6pm) |
No Homework |
Ckpt #2: AC97 Audio (Due) Lec #10: Ethernet [PDF] [] |
||
30 Mar |
Midterm II (Info: [PDF], Solution: [PDF], Grade Distribution: [PDF]) | |||
Testing, Fault Models, Design for Test [PDF] [] |
||||
State Machine Optimization, State Encodings,
and State Assignment [PDF] [] |
HW #8 [PDF] |
Ckpt #3: Ethernet [ZIP]
Lec #11: SDRAM & Routing [PDF] [] |
||
State Machines, Signalling, Metastability, Arbiter Design,
Hazards [PDF] [] |
||||
Arithmetic Circuits: Building Blocks [PDF]
[] |
Ckpt #4: SDRAM & Routing (2 weeks) [ZIP] Lec #12: Routing & Design Integration [PDF] [] |
|||
Arithmetic Circuits: Combinational and
Sequential Multiplier [PDF] [] |
||||
Evolution of FPGA Architectures [PDF]
[] |
HW #10 [PDF] |
Ckpt #4: SDRAM & Routing (Due) Lec #13: Final Checkoff and The Report [PDF] [] |
||
No Lecture. |
||||
14 |
26 Apr | Project Early Checkoff Deadline (Files due @ 10am) |
No Homework |
Lab: Final Integration and Project Demonstration |
Special Topics [PDF] [] |
||||
3 May | Project Final Checkoff Deadline (Files due @ 10am) |
Lab: Final Report [DOC] |
||
7 May |
Project Report due @ 4pm in 125 Cory |
|||
16 |
12 May | Final Review (in the lab 125Cory @ 4-7pm) (Slides: [PDF], Whiteboard: [ZIP], Video: []) |
||
Final Exam, 12:30-3:30 in 10 Evans (BRING
2 BLUE BOOKS ) |
Last Updated: 01/23/2005 by | [an error occurred while processing this directive] |
Greg Gibeling |