Outline of Topics Covered by Midterm Exam:

Introductory Material:

Concept of Hierarchy in designs and example hierarchies.

Concept of cost/performance/power tradeoffs and simple 
examples.


Combinational Logic Basics:

Function of primitive logic gates.  Derivation of truth tables
from simple combinational logic circuits.

Signal restoration and its importance in digital circuits.

Operation and implementation of multiplexors.


FPGAs:

Idealized FPGA architecture model.

Details of basic FPGA PIP (programmable interconnection point).

LUT implementation details.  Hierarchical LUT designs.

Partitioning logic circuits into LUTs and CLBs.

High-level details of Virtex 5 FPGAs (as presented in class).


State Elements and Sequential Circuits:

Basic flip-flop operation.  Flip-flop Input/output/clock timing and
constraints.  Flip-flop reset types and functions.

"Register transfer" notion of sequential circuit timing.  Waveform
diagrams.  Pipelining and signal feedback.

Level-sensitive latch operation.   Implementation of flip-flops
using level sensitive latches.

Flip-flop operation of Virtex 5 FPGA.


Verilog HDL:

Concept of "behavior" versus "structural" description.

Module specification and instantiation.

Basics of combinational logic and sequential circuit specification.

Continuous assignment versus procedural assignments (both blocking
and non-blocking).

Specification of Finite State Machines.

Use of module parameters and "generate" constructs.

Basic steps of logic synthesis and examples of how Verilog specifications
are converted to circuits.

Case versus nested If-else.

Differences between HDL for synthesis and for simulation.

Techniques for writing test-benches in Verilog.


Physical Design:

Chip-level design alternatives and pros and cons of each.

Economics of FPGAs versus ASICs.

CMOS circuits for basic logic gates, multiplexors, and flip-flops.
CMOS transmission gates.

Implementation of tri-state buffers and their use for bidirectional 
communication.


CPU microarchitecture:

Implementation of a single-cycle processor from ISA description.

Processor pipelining: impact on performance, hazard types and resolution.

Detailed operation of 3-stage MIPS pipeline.

Serial communication and UART basics.

Memory mapped CPU I/O and polling implementation.


Memory Blocks:

Naming conventions.

Internal organization.

SRAM Cell implementation.

Multiported memory internal organization.

Cascading memory blocks to increase width/depth/number of ports.

Virtex 5 block-RAM and LUT-RAM details and differences.

Operation and implementation of FIFO memories.


Video:

Basics of Video display subsystem, with framebuffer
and color map.

Decoupling CPU framebuffer writes from Video display.

Line drawing acceleration algorithm operation.


Ethernet:

Ethernet frame organization.

Concept of packet "encapsulation" and protocol stacks.

Hardware network interface organization.


Timing:

Relation of clock speed to performance.

Determination of maximum clock frequency from circuit.

Origin of logic delay.

Origin of flip-flop delay.

Wire delay and mitigation.

Effects of clock skew.