Computer Science 150:
Components and Design Techniques for Digital Systems

Prof. John Wawrzynek

Chris Fletcher
Ilia Lebedev
Brandon Myers
Kyle Wecker

Spring 2010 - Honors Section

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Lectures: Tuesday and Thursday, 2:00-3:30PM, 306 Soda
Lab Lecture: Friday, 2:00-3:00pm, 125 Cory

This semester, the course staff is offering an honors section in addition to regular discussions. The honors section will meet every Friday at 1pm and cover a broad range of subjects intended to place CS150 in the context of recent research, industrial, and economic developments. As part of the honors curriculum, we will assign extra reading material, expose you to material not normally covered in CS150, and expand the course project (with up to 1 checkpoint of extra work). The section will be taught jointly by Ilia Lebedev and Chris Fletcher.

If you are interested in participating, but are unable to attend, please contact Ilia. All are welcome, though the extra assignments are required to qualify you for extra credit.

Reading assignments are posted below, and will consist of 1-2 short papers a week. Most assignments will come from academic publications, with an occasional datasheet excerpt, or even a marketing publication.
The weekly assignment associated with each paper is as follows:

For each paper assigned, briefly address the questions below and send your responses to this address.

  1. Your name, login and SID
  2. Briefly connect the ideas in this paper to CS150. What did you learn from reading this paper (1-2 sentences per paper):
  3. One criticism of the ideas presented (1-2 sentences per paper):
  4. What idea presented in this paper would you like to hear more about? (1-3 sentences per paper)
  5. Rank the overall quality of the paper (1-10, for each paper):

Note that these questions are given to guide your reading. Do not waste your time writing essay responses. One or two sentences on each point are plenty (~20 min for all questions after reading).

Honors Assignments
Week Topic Due Date Assignment
1 - Fri 1/22 -
2 - Fri 1/29 -
3 Introduction to the FPGA; The D Flip Flop Fri 2/5 -
4 Using the FPGA for more than prototyping. FPGA accelerators, FPGA computing. Fri 2/12 Xilinx Xcell issue 69, p16-17.
Xilinx Xcell issue 67, p4.
Xilinx Xcell issue 59, p8-11.
A view of the parallel computing landscape, Asanovic et al. (skip the "ParLab is awesome" sections). All ACM papers are available from within the campus network. Use the UC Berkeley library proxy (google it), or download the paper using a campus machine.
5 Microcode Engines (How not to design a processor in CS150). Fri 2/19 Measuring the Gap between FPGAs and ASICs - Note: although there are many details that hinge on understanding of topics somewhat outside CS150, pay attention to the big picture.
CHIMPS - Note: This document will be removed after next week.
Reading responses are due by the date listed. See the top of this page for instructions.

To get some practice writing microcode, write a few crazy instructions in the handout here (credit : CS152 staff, and all entities acknowledged in the linked documents).
If you are particularly proud of your unholy instruction, send it to me (Ilia) with a short description of possible uses.
Please note that this is not directly applicable to CS150, and is simply meant to give you perspective. This will probably not help you review CS150 material.
6 Synchronous pipelines and synchronous flow control
[PDF 1P]		 Fri 2/26 SCORE p1-24. As always, reading responses are due by the date listed.

There was some discussion about the Virtex-6 CLB during this week's discussion. ug364.pdf is the Virtex-6 CLB user's guide. If you look on p10, you will see the extra set of flip-flops in each CLB. Notice that these flip-flops can be connected to the select bits that enable the 7-input and 8-input LUTs (that you are already familiar with). So, if you can give up the larger LUTs in your design, you can use these flip-flops as pipelining elements as was discussed.
7 Metastability, synchronizers, and asynchronous flow control
[PDF 1P]		 Fri 3/5 Clock Crossings p1-5.
High-Speed, Hierarchical Synchronous Reconfigurable Array
8 DRAM: bit cells to memory command scheduling Fri 3/12 If you are really interested in the DRAM interface, yet another possibility for additional project extra credit might be implementing a full 24-bit framebuffer (maybe even with dobule buffering) using the DRAM on the XUPv5 board.

For the honors project, you will accelerate scanline rasterization instead of line drawing.
There will be a small amount of hand-holding through this checkpoint, but you are largely on your own.
A software reference for this operation can be found here.
Although we have not yet posted the interface specification for this assignment, start thinking about the high-level structure of the accelerator.
9 Research Q&A, Bayesian Networks on FPGAs
[PDF 1P]		 Fri 3/19 Clock Crossings p5-7.
10 Spring Break Fri 3/26 No discussion. Optional readings:
  1. Optimal 90nm adder
  2. Power6 processor
  3. Intel Nehalem on FPGA(s)
11 Honors Project Introduction Fri 4/2 TBA
12 Standard Cell ASIC tool demo (Your Checkpoint 1 as a 90nm CMOS chip)
A brief introduction to systolic arrays.		 Fri 4/9 Work on your project!
Find a well-commented, simplified digital discrete analyzer algorithm (for your triangle engine) and verilog template here.
13 Honors Project Design Discussion Fri 4/16 TBA
14 Synchronous and asynchronous FIFOs
[PDF 1P]		 Fri 4/23 Here are the papers/tech. reports from the discussion. Try your hand at a Verilog asynchronous FIFO!
  1. Simulation and Synthesis Techniques for Asynchronous FIFO Design
  2. Simulation and Synthesis Techniques for Asynchronous FIFO Design with Asynchronous Pointer Comparisons
15   Fri 4/30 TBA
16   Fri 5/7 TBA

Please do not hesitate to contact us in Office Hours or by e-mail with any questions.

maintained by Ilia Lebedev : ilial(at)berkeley(dot)edu
Copyright UC Berkeley EECS150 http://inst.eecs.berkeley.edu/~cs150/sp10/