# More Practice Problems

1. Consider the following CPU (bold lines indicate busses):

The outputs from the four registers R1-R4 are controlled by tristate drivers (E1-E4); a 1 on these control signals will output the register value onto the appropriate bus. A special register "0" always outputs the value 0, and the tristate drivers for this register allow 0 to be output onto either operand bus. The registers have clock enables (L1-L4) which force the registers to load the value from the ALU output bus (BUSx) on the upcoming clock tick (clocks not shown). The output of the ALU is selected by a multiplexer (SS); a 0 on this control selects the result from an adder/subtracter unit (AS=0 chooses addition (BUSa+BUSb); AS=1 chooses subtraction (BUSa-BUSb)). When SS=1, the ALU output comes from a shift unit which takes the data on BUSb and shifts it left by 1 (putting 0 in the LSB); this is indicated using the notation <<1. Assume all arithmetic is performed on unsigned quantities; ignore any overflow conditions.

Show how the following instructions (operations) can be implemented using this CPU structure. Indicate the control signals which need to be applied. Some of these instructions require more than one cycle to execute. No register may be overwritten during the execution of any instruction, except (of course) the destination register for the operation.

1. R3 := R1 + R3
2. R4 := R3
3. R4 := R1 - R2
4. R2 := R4 << 1
5. R3 := R2 * 2
6. R3 := (R2 + R4) << 1
7. R3 := R2 * 3
8. R4 := (R1 + R2) * 3

2. (From M.Mano, Digital Design, 2nd ed., p. 394)
Consider the following circuit:

1. Derive next-state functions for the signals Y1,Y2. Hint: consider the cross-coupled NAND gates as S-R latches. Note that the 3-input NAND gate should be decomposed into a 2-input AND and a 2-input NAND before considering it as part of an S-R latch, since the S-R latch uses 2-input NAND gates only.
2. Give a flow table for this circuit. Remember to indicate all stable positions in the table.