University of California at Berkeley | ||
College of Engineering | ||
Department of Electrical Engineering and Computer Sciences | ||
CS 150, Spring 1997 | Prof. R. Newton | |
February 7, 1997 | Phillip Chong | |
Lab 3 |
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Finite State Machine on Xilinx |
Put your combination lock from Lab 2 onto a chip. To do this, you will
For a design to be useful, it must make its way into hardware. To do this we will be using Xilinx Field Programmable Gate Arrays (FPGAs), chips that can be configured as many different circuits. Specifically, we will be using the Xilinx XC4000 Design Demonstration Board, which contains an XC4005 FPGA, switches, and light-emitting diodes.
These boards are very expensive and not easily replaced. Be very careful with these. Make sure that they stay on the anti-static mat. Make sure also that the ground plug is plugged in. Before touching the Xilinx board, ground yourself: touch any metal you can find or the static mat.
For now, do not take the Xilinx boards or anything else from 204B Cory!
To compile your design for the Xilinx, some interface components need to be added. We have done the busy work for you. Look at the design at your leisure.
I/O pads and buffers are special cells in the (xc4000) library, connect the Xilinx to the outside world of buttons, LEDs, and other chips:
IPAD | Input Pad | OPAD | Output Pad |
IBUF | Input Buffer | OBUF | Output Buffer |
Each IPAD and OPAD is connected to a particular pin on the Xilinx, designated by the LOC attribute. For example, in our schematic, the IPAD in the upper-left corner, SW5-1, has the attribute LOC=P27, indicating it connects to pin 27 of the Xilinx.
Your lock expects ENTER and RESET to be high for exactly one clock cycle every time it is pressed. The DEBOUNCE circuit, a simple state machine, ensures this.
We have entered the required interface circuits; you need to copy them into your design. We'll use the ability of ViewDraw schematics to be divided into sheets.
A single schematic, i.e., one that can be enclosed in a symbol, can be divided into multiple sheets. Until now, you have only used one-sheet schematics (hence the .1 extension on their names). To add the interface circuitry, we will put it on a second sheet.
Like on one-sheet schematics, nets with the same label on different sheets of the same schematic are connected implicitly.
XMake compiles your schematic into a form that can be downloaded into a Xilinx FPGA. This process can take up to fifteen minutes for this lab. The flow is shown in Figure 1.
If errors occur during XMake, check the .OUT and the .PRP files. At least fifteen other files are also created, of varying utility. The .RPT file is interesting if the XMake is successful.
Figure 1. XMake's flow
XChecker is Xilinx's real-time hardware debugging tool, something like gdb for debugging hardware. The XChecker program communicates with the XC4000[A] through the XChecker cable. Table 1 (below) lists some useful XChecker commands.
load design | Download design.BIT to the FPGA |
clock -int | Use the XChecker clock |
clock -ext | Use an external clock |
clock -stop | Stop the XChecker clock |
clock -resume | Enable the XChecker clock |
clock -speed n | Set the speed of the XChecker clock. The slowest is 1 (about 920 kHz) |
clock n | Step n clock cycles |
help | List XChecker commands |
quit | Terminate XChecker |
The power supplies have a cable with two banana plugs, red and black, and a yellow lead. The black is ground, the red is +5V, and the yellow is -5V. Don't attach the -5V connector to anything, and make sure it doesn't touch anything metal!
U: |
CD \userlogin \lab2 |
XCHECKER |
Have your TA check off your working lock.
Try stopping and restarting the clock: