Name: _______________________________________ | Name: _______________________________________ |
Lab Section: |
What is ENTER connected to (include direct and indirect sources)? Why? |
What do you expect to see to see when the lock is opened? |
To where does the clock feed out? Why? |
Why are CODE0 and CODE1 not debounced? |
In terms of buttons, switch settings, and lights illuminating, give instructions for opening the lock. |
Explain the three wire-wrap wires on the board. Why are they there? Why does SW 4-7 have to be closed? (Hint: look at a board and the demonstration board schematics) |
By looking at the report files, how many CLBs does your design use? |
1. Working Xilinx Lock |
TA: |
___________________ (50%) |
2. Questions answered |
TA: |
___________________ (40%) |
3. Turned in on time |
TA: |
___________________ (10%) |