If you find something wrong with these solutions,
please post it to the news group and mail
Tina at tinas@cory.eecs.
(1) a) Convert the BCD coded number below to equivalent decimal form:
1000011101100010.01100101
BCD uses enough bits
to represent any value from 0 to 9 ( in other words 4 bits )
to represent one digit.
So divide up a number into 4 bit groups:
1000-0111-0110-0010.0110-0101
then change each group
to its decimal value:
8762.65
b) Convert (271.A)base 16 to
i) Convert each digit of
the base 16 number to base 2:
2 = 0010
7 = 0111 etc...
271.A
base 16 => 001001110001.1010 base 2
ii) Convert each digit of
the base 16 number to base 8:
Group
the bits of the base 2 number into groups of three starting from the
decimal
point and you get:
001001110001.1010
base 2 => 1161.5 base 8
c) Design a circuit for converting a 4-bit Gray code into its binary equivalent.
You may use AND, OR, XOR, or inverter gates only. Use as few gates as possible.
Gray Code | Binary Equivalent |
0000 | 0000 |
0001 | 0001 |
0011 | 0010 |
0010 | 0011 |
0110 | 0100 |
0111 | 0101 |
0101 | 0110 |
0100 | 0111 |
1100 | 1000 |
1101 | 1001 |
1111 | 1010 |
1110 | 1011 |
1010 | 1100 |
1011 | 1101 |
1001 | 1110 |
1000 | 1111 |
Logic for BE ( Binary Equivalent ) from GRAY code values:
BE3:
GRAY10/GRAY32
00 | 01 | 11 | 10 | |
00 | 0 | 0 | 1 | 1 |
01 | 0 | 0 | 1 | 1 |
11 | 0 | 0 | 1 | 1 |
10 | 0 | 0 | 1 | 1 |
BE3 = GRAY3
BE2:
GRAY10/GRAY32
00 | 01 | 11 | 10 | |
00 | 0 | 1 | 0 | 1 |
01 | 0 | 1 | 0 | 1 |
11 | 0 | 1 | 0 | 1 |
10 | 0 | 1 | 0 | 1 |
BE2 = 'GRAY3 GRAY2 + GRAY3 'GRAY2 = GRAY3 xor GRAY2
BE1:
GRAY10/GRAY32
00 | 01 | 11 | 10 | |
00 | 0 | 1 | 0 | 1 |
01 | 0 | 1 | 0 | 1 |
11 | 1 | 0 | 1 | 0 |
10 | 1 | 0 | 1 | 0 |
BE1 = 'GRAY3 GRAY2 'GRAY1 + GRAY3 'GRAY2 'GRAY1 + 'GRAY3 'GRAY2 GRAY1 + GRAY3
GRAY2 GRAY1
= GRAY3 xor GRAY2 xor GRAY1
BE0:
GRAY10/GRAY32
00 | 01 | 11 | 10 | |
00 | 0 | 1 | 0 | 1 |
01 | 1 | 0 | 1 | 0 |
11 | 0 | 1 | 0 | 1 |
10 | 1 | 0 | 1 | 0 |
BE0 = (Using '(A xor B) = 'A'B + A B )
= GRAY3 xor GRAY2 xor GRAY1 xor GRAY0
d) Implement a 1-bit adder using a minimum number of 4-input,
2-control multiplexers
and inverters only. An inverter
counts as 1/5th of a multiplexer. Assume complements
are not available.
(2) Describe the function and characteristics of the JK counter circuit (that was in the hw).
SEE MESSAGE IN THE NEWS GROUP!!!! ( 4/6 1:30pm )
(3) A JN flip-flop has two inputs, J and N. Input J behaves like
the J input of a JK flip-flop, and N behaves
like the complement of the K input of a JK flip
flop ( i.e. N = 'K ).
(i) Obtain the characteristic table
of the JN flip-flop
J | K | N('K) | Next Q |
0 | 0 | 1 | Q |
0 | 1 | 0 | 0 |
1 | 0 | 1 | 1 |
1 | 1 | 0 | 'Q |
Rewriting the table with just J and N we get:
J | N | Next Q |
0 | 0 | 0 |
0 | 1 | Q |
1 | 0 | 'Q |
1 | 1 | 1 |
Which, I believe, is the characteristic table.
(ii) Show that by connecting the two J and
N inputs together, one obtains a D-type flip-flop.
Well, when the J and N inputs are tied together J = N. And by
looking at the characteristic table in part (i),
we see that when J = N = 1, the next Q is 1, and when J = N
= 0, we see that the next Q is 0 which is
exactly the behavior of a D flip-flop.
(4) This problem was a problem on the Spring '94 midterm, uh, I mean quiz #2.