Bussing Strategies
Multiple Busses
Example Register Transfer for Single Bus Design
IR<operand address> ? BUS;
BUS ? MAR;
Memory Read;
Databus ? MBR;
MBR ? BUS;
BUS ? ALU B;
AC ? ALU A;
ADD;
ALU Result ? BUS;
BUS ? AC;
Fetch Operand
Cycle 1:
Cycle 2:
Perform ADD
Cycle 3:
Write Result
Cycle 4:
Instruction Interpretation for "ADD Mem[X]"
Requires latch
for ALU Result
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