Bussing Strategies
Multiple Busses
Instruction Interpretation for "ADD Mem[X]"
IR<operand address> ? ABUS;
ABUS ? MAR;
Memory Read;
Databus ? MBR;
MBR ? MBUS;
MBUS ? ALU B;
AC ? ALU A;
ADD;
ALU Result ? RBUS;
RBUS ? AC;
Fetch Operand
Cycle 1:
Cycle 2:
Perform ADD
Cycle 3:
Write Result
Implemented
in three cycles
rather than four
Advantage of separate ABUS:
overlap PC ? MAR with instruction execution
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