Deriving the State Diagram and Datapath
State Machine Inputs and Outputs so far:
Inputs:
Reset
Wait
IR:14>
AC>
Outputs:
0 ? PC
PC + 1 ? PC
PC ? MAR
MAR ? Memory Address Bus
Memory Data Bus ? MBR
MBR ? Memory Data Bus
MBR ? IR
MBR ? AC
AC ? MBR
AC + MBR ? AC
IR:0> ? MAR
IR:0> ? PC
1 ? Read/Write
0 ? Read/Write
1 ??Request
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