Design Example 1: Word Problem
? An asynchronous network has two inputs and one output. The input sequence X1X2 = 00, 01, 11 causes the output, Z, to become 1. The next input change then causes the output to return to 0. No other input sequence will produce a 1 output.
Fundamental mode, single input changes, so input can only change in stable total state and only one bit can change, so this total-state is impossible, since only stable total state is inputs 00 in this row.