Completion of the Output Table
a 00 00 00 10 01 0 0 - 0v
b 01 00 01 01 01 0u 0 0 0
From State 00, input change 00-ᡂ causes transition to stable state 01. To avoid glitch if logic synthesis assigns "don't care" in output to 1 for input value 10, make it a 0 (labelled v above).
From State 01, input change 01-ᠸ causes transition to State 00, so avoid possible glitch by assigning output in State 01 for input 00 to 0 (u above)
From State 10, input change 11-ᠹ causes transition to stable state 01, via 11. Since output goes from 1 to 0, choose output at t above to be 1, consistent with the starting value, but leave output at s a "don't care" since must make the transition somewhere and either before or after State 11 is the same.