3-bit Parity Function:Possible VHDL Implementation
ENTITY parityFunction IS
PORT( A, B, C : IN t_wlogic; parity : OUT t_wlogic )
ARCHITECTURE full OF parityFunction IS
BEGIN
PROCESS (A, B, C)
VARIABLE count : integer;
BEGIN
count := 0;
IF A = '1' THEN count := count +1; END IF;
IF B = '1' THEN count := count +1; END IF;
IF C = '1' THEN count := count +1; END IF;
IF (count MOD 2) = 0 THEN
ELSE
END IF;
END PROCESS;
(Adapted from D. R. Coelho, "The VHDL Handbook," Kluwer, 1989)