Checkpoint 1 - Serial Sender
In this lab, you will be making the serial sender that you will later be using in your project to
send data to the computer. The FSM that will control the transmitter is fairly easy compared
to Lab 7 or some of your homework assignments. The only hard part may be implementing a
clock divider that works correctly in hardware.
- You have to have your project overview done by the time you meet with your TA. You will need
to have a copy for your TA as well.
- For your prelab, you will need to have your Maxim wire-wrapped and a simultion in ViewSim and VWaves
that shows the sending of 1 byte of data with the start and finish bits in the right place. The
prelab is worth 45% of the checkpoint grade!
- To test your wiring, you can download the U:\WVLIB\CS150\UART.BIT file to your Xilinx board and then
run the U:\WVLIB\CS150\PTEST.EXE program to test reading. You will need to connect the serial cable
to the correct pin. There are three lines coming out of the serial cable; one connects to one of the
T out lines on the Maxim chip, the middle connects to nothing, and the last connects to ground.
- To run PTEST.EXE, you will need to set a few options. If you are in 123 Cory, you will have to
type in COM4 at the prompt and COM2 if running the program in 204B Cory. Then you will need to set
the options from the options menu: Baud is 115200, timeout is 20, output is hex, and the parity is
set to the first choice.
-
You should not change the names of signals on the TA provided schematic. You should leave it as it is and make your
signals match those on the TA schematic.
- You will need to send data over the serial port at about 115.2KHz, so you can either run
your whole FSM at the slow clock or just enable your shift registers at specific times. It is
probably easier to have your whole FSM run at the slower clock, since it may be easier
to debug.
- If you get an error about PULLDOWN when you are running ViewVSM, you should remove the
the readback block from the TA schematic. After you are done simulating, you may want to
return the readback block if you want to be able to use the Xilinx debugging features.
- Simulating your clock divider may be difficult, since you will have to reset the counter used
in the clock divider. The reason this may be difficult is that the signal called RESET is
sent through the debounce circuit which is clocked by the slow clock. So, you may have a clock
divider that works perfectly in a simulation but doesn't work in hardware. In hardware, you will
not have to reset your clock, since it will start at some defined value and eventually get to
zero.
- You can use your logic probe to test if you clock divider is working in hardware. If you
probe pin 8 on the Xilinx, the logic probe should show a signal that is pulsing. If it is
high or low only then you have a problem.
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