Lab 2 - Finite State Machine in Workview

This lab should take longer than three hours, so do as much as you can before the lab. I recommend that you complete Lab 1 if you have not already done so, because it will get you familiar with all of the software you will use in Lab 2. As before, read the entire lab handout before reading this and before starting the lab.

This weeks lab shouldn't be difficult, but it may take some time to enter the schematics.

• Remember to only use components from the XC4000E library. This will avoid problems for next week's lab when you download your schematics onto the Xilinx board.
  
  
• When creating your symbol and naming a bus, answer NO to the question about Expanding the label. The default is YES, so be careful.
  
  
• For MYCLB, you just have to implement the equations that are given to you.
  
  
• The ' symbol in the logic equations for MYCLB are inversions.
  
  
• You will need to make a bus for NS and S in MYCLB and in MYDFF.
  
  
• All busses need to be labeled, even if they go directly from one component to another component.
  
  
• Remember to keep your schematics neat and readable. Always put nets and their names on the left connect to components on the right (left to right) or top to bottom. The TAs can grade your schematics on style, so ask your TA if you have any questions about style.
  
  
• As before, Save + Check your schematics instead of Save. Also do this to the schematic after finishing your symbol, since it will tell if you messed up when making the symbol and/or schematic.
  
  
• You will need to test the schematic using ViewSim. It is a little tricky to get the circuit in a state where everything is 0 instead of undefined, because of the Flip Flops which will only change when the clock is high. So, in ViewSim, you will have to define a clock using the command "clock clk 0 1" where clk is the net you connected to the clock in MYDFF. Then you will have to use "cycle" instead of "sim" to simulate each time step. Now you should be able to use the FFRESET net and the "cycle" command to reset your states to zero. After you have done that, type in "r FFRESET" to release the net. You shouldn't have to touch FRESET again during the simulation.
  
  
• When testing the schematic, remember that ENTER must be high after setting the code (just like pressing ENTER after punching in a code). You will need to use the "cycle" command in the right place in your simulation for everything to work properly.