CS 152
Computer Architecture and Engineering
CS152 Fall 2004
TuTh -- 11 AM to 12:30 PM
320 Soda Hall

Dave Patterson | John Lazzaro
Douglas Densmore | Ted Hong | Brandon Ooi

News and Calendar | Course Info | Resources | Staff | WebNews | WebGrades | Projects | MIPSASM
Resources and Links

Links to References:

  • Sample Online Notebook: [html]
  • Lab Report Format: [html]
  • Documents:
    • Paper on testing by Douglas Clark: [ps,pdf]
    • From ASIC to ASIP: The Next Design Discontinuity,
      by Kurt Keutzer, Sharad Malik, and Richard Newton. [pdf]
    • A Case for Redundant Arrays of Inexpensive Disks (RAID),
      by David A. Patterson, Garth Gibson, and Randy H. Katz. [pdf]
    • The optimal logic depth per pipelining stage is 6 to 8 FO4 inverter delays,
      by Hrishikesh, M., Jouppi, N., Farkas, K., Burger, D., Keckler, S., and Shivakumar, P. [pdf]
    • IBM Power 5 Chip: A Dual-Core Multithreaded Processor,
      Ron Kalla, Balaram Sinharoym, Joel M. Tendler [pdf]
    • Improving Direct-Mapped Cache Performance by the Addition of a Small Fully Associative Cache and Prefetch Buffers.,
      by Norman P. Jouppi [pdf]
    • Lockup-Free Instruction Fetch/Prefetch Cache Organization,
      by David Kroft [pdf]
    • Alternative Implementation of Two Level Adaptive Branch Prediction,
      by Tse-Yu Yeh and Yale Patt [pdf]
    • The Bi-Mode Branch Predictor,
      by Chih-Chieh Lee, I-Cheng Chen, and Trevor Mudge [pdf]
  • SPIM Documentation [ps, pdf]
  • MIPS Instruction Set Reference [pdf]
  • Information about the Calinx boards that we will be using: [html]
    • Xilinx VIRTEX E FPGA Databook [pdf]
    • 128 Mb SDRAM technical manual [pdf]
    • 256 Mb SDRAM technical manual [pdf]
  • CVS Information:
    • Michael Chu's quick CVS tutorial [txt]
    • John Gibson's CVS on Windows tutorial [html]
  • Verilog information:
    • IEEE Standard Verilog Hardware Description Language (Berkeley only) [pdf]
    • Verilog Tutorial (from Bucknell University) [html]
    • Discussion of blocking and non-blocking assignments. [pdf]
  • Modeling Delays in Verilog [pdf]
  • Xilinx Tool information (Berkeley only):
    • Xilinx manuals on line [pdf]
    • ModelSim manual [pdf]
    • Synplify Reference Manual [pdf]
    • Xilinx Tutorial #1 (Tool Flow) [doc]
    • Xilinx Tutorial #2 (Global Time Constraints) [doc]
    • Xilinx Tutorial #3 (XST Synthesis) [doc]
    • Xilinx Tutorial #4 (Coregen) [doc]
    • Xilinx Tutorial #5 (Floorplanner) [doc]
    • Xilinx Tutorial #7 (HDL Bencher) [doc]
    • Xilinx Tutorial #8 (Pong) [doc]
    • Xilinx Tutorial #9 (StateCAD) [doc]
    • Xilinx Tutorial #10 (Detail Design Description) [doc]
  • Xilinx support websites [support.xilinx.com]
  • MSU's Xilinx's support page [xup.msu.edu]
  • Remote Desktop Connection Information [doc]
  • Tutorial For the Xilinx Tool Flow (From CS152 TA alumni): [pdf, doc]
  • Specs for exception handling [txt]
  • Past Exams:
    • Fall 2003 Midterm #1 [pdf]
    • Fall 2003 Midterm #1 Solution [pdf]

© 2004 UCB http://www-inst.eecs.berkeley.edu/~cs152/