Welcome to the Fall 06 CS 152 web page. The Lab handouts and homework assignments for Fall 06 are linked in the calendar below, as are slides for the first few weeks of lecture (covering the material needed for Labs 1 and 2).

Note that for Fall 06, completion of EECS 150 at UC Berkeley is a requirement for undergraduates to take CS 152. Completion of a logic design course at another university is NOT sufficient -- you MUST take EECS 150 here BEFORE taking CS 152. This requirement reflects how closely the CS 152 project relies on CAD tool training and Verilog project skills developed in EECS 150.

Graduate students are exempt from the EECS 150 requirement. However, graduate students should consider that CS 152 has a very demanding project component -- for many graduate students, devoting this much time to one course is not appropriate. In addition, grading will be done on the undergraduate curve (mean grade of 2.9-3.3) -- we will not be grading graduate students on an easier curve. That being said, graduate students committed to architecture, embedded systems, or CAD who are confident of their digital design and Verilog skills may find CS 152 to be a good investment of their time.