CS 152
Computer Architecture and Engineering
CS 152 Fall 06
TuTh -- 11:00 to 12:30 PM
310 Soda Hall

John Lazzaro | Udam Saini | Jue Sun

News and Calendar | Course Info | Resources | Staff | MIPSASM
 
Announcements
8-25-2006

Welcome to the Fall 06 CS 152 web page. The Lab handouts and homework assignments for Fall 06 are linked in the calendar below, as are slides for the first few weeks of lecture (covering the material needed for Labs 1 and 2).

Note that for Fall 06, completion of EECS 150 at UC Berkeley is a requirement for undergraduates to take CS 152. Completion of a logic design course at another university is NOT sufficient -- you MUST take EECS 150 here BEFORE taking CS 152. This requirement reflects how closely the CS 152 project relies on CAD tool training and Verilog project skills developed in EECS 150.

Graduate students are exempt from the EECS 150 requirement. However, graduate students should consider that CS 152 has a very demanding project component -- for many graduate students, devoting this much time to one course is not appropriate. In addition, grading will be done on the undergraduate curve (mean grade of 2.9-3.3) -- we will not be grading graduate students on an easier curve. That being said, graduate students committed to architecture, embedded systems, or CAD who are confident of their digital design and Verilog skills may find CS 152 to be a good investment of their time.

 
Assignment and Lecture Calendar
Notes:
  • All reading refers to sections in COD unless noted otherwise.
  • Lecture notes are available in PDF format (one slide per page).
  • PPT exported from Keynote and may show visual artifacts in PowerPoint.
Wk Date Lecture Topic Notes Reading Assignment
1 M
8/28
T
8/29
The MIPS ISA PDF PPT Ch 2, 3.1-3, 3.8 Start on Lab 1; Preview Lab 2
W
8/30
HW 1 and solution
(due at Midterm I review session)
Th
8/31
Single-Cycle Datapaths PDF PPT 5.1-4, 5.8, Appendix B
F
9/1
Teams Meet the TAs, 12-2 or 3-5 PM, 125 Cory
Sa
9/2
Su
9/3
2 M
9/4
(Labor Day Holiday)
T
9/5
Single-Cycle Wrap-Up + VLIW PDF PPT Review papers on MultiFlow VLIW architecture and compiler. Lab 1: Final Report Due, 11:59 PM,
via the submit program
W
9/6
Th
9/7
Testing and Teamwork PDF PPT Lab 2: Preliminary Design Document due to TAs, 11:59PM
F
9/8
Lab 2: Design Document Review, 12-2PM or 3-5PM, 125 Cory
Sa
9/9
Su
9/10
3 M
9/11
Lab 2: Final Design Document due to TAs, 11:59PM
T
9/12
Timing PDF PPT
W
9/13
Th
9/14
Performance and Energy PDF PPT 5.5, 5.7
F
9/15
Lab 2: ModelSim Checkoff, 12-2PM or 3-5PM 125 Cory
Sa
9/16
Su
9/17
4 M
9/18
T
9/19
Pipelining I PDF PPT 6.1-4 Preview Lab 3
W
9/20
Th
9/21
Pipelining II PDF PPT 6.5-7
F
9/22
Lab 2: Xilinx Checkoff, 12-2PM or 3-5PM, 125 Cory
Sa
9/23
Su
9/24
5 M
9/25
Lab 2: Final Report due, 11:59 PM, via the submit program
T
9/26
Pipelining III PDF PPT 6.8-9
W
9/27
Th
9/28
Midterm Review Session in Class PDF PPT HW 1 due in class (solution here)
Lab 3: Preliminary Design Document and Team Evaluations due to TAs, 11:59PM
F
9/29
Lab 3: Preliminary Design Document Review, 12-2PM or 3-5PM, 125 Cory
Sa
9/30
Su
10/1
6 M
10/2
T
10/3
Midterm I: 6:00PM to 9:00PM, 306 Soda (HP Auditorium)
(note: no class 11-12:30)
W
10/4
Lab 3: Final Design Document due to TAs, 11:59PM
Th
10/5
VLSI PDF PPT HW 2 and solution
F
10/6
Lab 3: Initial Xilinx Checkoff, 12-2PM or 3-5PM, 125 Cory
Sa
10/7
Su
10/8
7 M
10/9
T
10/10
Memory Circuits and Interfaces PDF PPT
W
10/11
Th
10/12
Cache I PDF PPT 7.1-2 Preview Final Project
F
10/13
Lab 3: Final Xilinx Checkoff, 12-2PM or 3-5PM, 125 Cory
Sa
10/14
Su
10/15
8 M
10/16
Lab 3: Final Report Due, 11:59 PM via the submit program
T
10/17
Cache II PDF PPT 7.3
W
10/18
Th
10/19
Virtual Memory PDF PPT 7.4-5, 7.7 Final Project: Preliminary Design Document due 11:59PM. Team Evaluations due 9PM.
F
10/20
Final Project: Preliminary Design Document Review, 12-2PM or 3-5PM, 125 Cory
Sa
10/21
Su
10/22
9 M
10/23
Final Project: Final Design Document due to TAs, 11:59PM
T
10/24
Error Correcting Codes PDF PPT 8.2
W
10/25
Th
10/26
Advanced Processors I PDF PPT 6.6, 6.9, Yeh and Patt branch prediction paper.
F
10/27
Final Project: DRAM Controller Xilinx Checkoff, 12-2PM or 3-5PM, 125 Cory
Sa
10/28
Su
10/29
10 M
10/30
T
10/31
Advanced Processors II PDF PPT 6.9-10
W
11/1
Th
11/2
Advanced Processors III PDF PPT
F
11/3
Final Project: Memory System Xilinx Checkoff, 12-2PM or 3-5PM, 125 Cory
Sa
11/4
Su
11/5
11 M
11/6
T
11/7
Buses, Disks, RAID, and Flash Memory PDF PPT 8.1-2, 8.4
W
11/8
Th
11/9
Networks and Routers PDF PPT 8.3, MGR Paper
F
11/10
(Veterans Day Holiday) No Checkoff
Sa
11/11
Su
11/12
12 M
11/13
T
11/14
Graphics Processors PDF PPT
W
11/15
Th
11/16
Synchronization PDF PPT
F
11/17
Final Project: Final Checkoff, 12-2PM or 3-5PM, 125 Cory
Sa
11/18
Su
11/19
13 M
11/20
Final Project: Final Report due, 11:59 PM, via the submit program
T
11/21
Multiprocessors PDF PPT
W
11/22
Th
11/23
(Thanksgiving Holiday)
F
11/24
(Thanksgiving Holiday)
Sa
11/25
Su
11/26
14 M
11/27
T
11/28
Guest Lecture:
Adam Megacz
PDF Final Project: Team Evaluations due to TAs, 11:59PM
W
11/29
Th
11/30
Midterm II Review in Class PDF PPT HW II due in class (solution here)
F
12/1
Sa
12/2
Su
12/3
15 M
12/4
T
12/5
Midterm II: 6:00PM to 9:00PM, 306 Soda (HP Auditorium)
(note: no class 11-12:30)
W
12/6
Th
12/7
Last Day: "Lessons Learned" Group Presentations Email Presentation Slides to Instructor by 11:59 PM
F
12/8
Sa
12/9
Su
12/10
 

© 2006 UCB http://www-inst.eecs.berkeley.edu/~cs152/