Welcome to the Fall 2016 CS152 web page. The course is intended to provide a foundation for students interested in performance programming, compilers, and operating systems, as well as computer architecture and engineering. Our goal is for you to better understand how software interacts with hardware, how hardware functions to provide you with the functionality you observe every day, and to understand how trends in technology, applications, and economics drive continuing changes in the field. The course will begin with basic processor design, proceed to advanced concepts found in modern products, then cover the different forms of parallelism found in applications (instruction-level, data-level, thread-level, gate-level) and how these can be exploited with various architectural features, and conclude with advanced topics on GPUs and emerging alternative architectures. We will cover pipelining, superscalar, speculative and out-of-order execution, vector machines, VLIW machines, multithreading, graphics processing units, and parallel microprocessors. We will also explore the design of memory systems including caches, virtual memory, and DRAM. Advanced topics include GPUs and alternative computational models such as neuromorphic. For more information please refer to the syllabus.

An important part of the course is a series of lab assignments using real microprocessor designs implemented in the Chisel hardware description language, and running as simulators of actual hardware. These simulators will give you an in-depth look at a variety of processor architectural techniques. Our objective is that you will understand all the major concepts used in modern microprocessors by the end of the semester.

Course Calendar with Handouts

Note: Tentative, schedule subject to change!
Pink means deadline. Yellow means quiz. Green means holiday.

Week Date Lecture Readings
5th Edition
4th Edition
1 Thu
Aug 25
L1: Introduction, Early Machines PDF Ch. 1, App. A Ch. 1, App. B
Aug 26
Section 1 PS 1 PDF (Solutions)
Handout PDF
Lab 1 PDF
2 Tue
Aug 30
L2: Simple Machine Implementations, Microcoding PDF Ch 3.13
Sep 01
L3: From CISC to RISC PDF App K.4 Register for Lab 1
Sep 02
Section 2
3 Tue
Sep 06
L4: Pipelining PDF App. C.1-C.3 App. A.1-A.3
Sep 08
L5: Pipelining II PDF App. C.4-C.6 App. A.4-A.6
Sep 09
Section 3 Lab 1 due
4 Tue
Sep 13
L5: Pipelining II (continued)
Sep 15
L6: Memory Hierarchy PDF App. B.1-B.2, Ch. 2.1-2.3 App. C.1-C.2, Ch. 5.1-5.3 PS 1 due
Sep 16
Section 4 PS 2 PDF (Solutions)
Handout PDF
Lab 2 PDF
5 Tue
Sep 20
Quiz 1: ISAs, microcode, simple pipelines
Sep 22
L7: Memory Hierarchy II PDF App. B.3 App. C.3
Sep 23
Section 5 Register for Lab 2
6 Tue
Sep 27
L8: Address Translation and Protection PDF App. B.4-7 App. C.4-7
Sep 29
L9: Virtual Memory PDF Ch. 2.4. App. B.4
Sep 30
Section 6
7 Tue
Oct 04
L10: Complex pipelines, Out-of-order Issue, Register Renaming PDF, PPT Ch. 3.1,3.4-3.5 Ch. 2.1,2.4-2.5 PS 2 due
Lab 2 due
Oct 06
Quiz 2: Memory Hierarchies and Virtual Memory
Oct 07
Section 7
8 Tue
Oct 11
L11: Out-of-order Exceptions, Branch Prediction PDF, PPT Ch. 3.6, 3.8 Ch. 2.6, 2.8 PS 3 PDF (Solutions)
Oct 13
L12: Advanced Out-of-Order Superscalars PDF(1), PDF(2) Ch. 3.7
Oct 14
Section 8 Lab 3 PDF
9 Tue
Oct 18
L13: VLIW PDF Ch. 3.2, 3.7 Ch. 2.2, 2.7 PS 3 due
Oct 20
Quiz 3: Complex Pipelining
Oct 21
Section 9 Register for Lab 3
10 Tue
Oct 25
L14: Multithreading PDF Ch. 3.12 Ch. 3.5 PS 4 PDF (Solutions)
Handout PDF
Oct 27
L15: Vectors PDF Ch. 4.1-4.3 (App. G) App. F
Oct 28
Section 10 Lab 3 due
11 Tue
Nov 01
L16: GPUs PDF Ch. 4.4-4.9 Lab 4 PDF
Nov 03
L17: Snoopy Caches PDF Ch. 5.1, 5.5-5.6 Ch. 4.1-4.4 PS 4 due
Nov 04
Section 11 Register for Lab 4
12 Tue
Nov 08
Quiz 4: VLIW, Vectors, Multithreading
Nov 10
L18: Directory Protocols PDF Ch. 5.2-5.3 PS 5 PDF
Handout 6 PDF
Handout 7 PDF
Solutions PDF
Nov 11
13 Tue
Nov 15
L19: Synchronization and Sequential Consistency PDF Ch. 5.4 Lab 4 due
Nov 17
L20: Power and Energy PDF Ch. 6 PS 5 due
Nov 18
Section 12 Lab 5 PDF
14 Tue
Nov 22
Quiz 5: Parallel Architectures
Nov 24
Nov 25
15 Tue
Nov 29
L21: Power (cont.)
Dec 01
L22: The Emerging Trends and Wrapup
Dec 02
Section 13 Lab 5 due