Homework 2 is due at the start of the lab section on Friday, 4/22. Please include your NAME, STUDENT ID and LOGIN on your homework.
No late homeworks will be accepted.
You may discuss problems with your friends, but all work must be done individually and you must be able to prove that you understand everything that you hand in.
If we can't read it from 2 feet away, we won't grade it.
This homework consists of a single, long design problem. You will do a paper design of the datapath and control for one line of a reorder buffer (described in the 4/7 lecture, and also in the readings for the lecture in the book). Below, we show the figure describing the reorder buffer:
By "line", we mean, for example, the row whose instruction number is 8 in this diagram.
We assume these fields are all stored in positive edge-triggered flip-flops connected to a common clock, each with a write-enable input.
Your design will be a listener on the common data bus: it will be snooping each transaction, seeing if the register number on the bus is a match for the #1, #2, or #d fields, and if so, potentially updating one of the following fields: E, P1 valid, P2 valid, Pd valid, P1 value, P2 value, Pd value.
The other reorder buffer fields (inst #, op, U, #1, #2, #d) are read-only for your unit. The instruction dispatch and instruction completion modules will act to write those fields (and perhaps some of the other fields -- in this problem, ignore how your module shares write access of those fields) when new instructions are added to the head of list, or taken off the tail of list.
Your module starts its tasks when it senses the U bit for the line is set to 1 and the Pd valid bit is set to 0 (the dispatch and completion modules write this bit, and all other bits, synchronous to the clock).
The module's task is broken up into two phases. In phase 1, it senses the common data bus for #1 and #2 values, and fills in the P1 valid, P2 valid, P1 value, and P2 value fields. Note that the instruction dispatch unit may fill in the P1 and/or P2 value fields, in which case the dispatch unit will set the P1 and/or P2 valid bits to 1. Once both P1 and P2 value fields are filled, your module sets the E bit, and phase 1 ends.
The execute module (an external mondule that you do not need to implement for this homework) monitors the E bit: once it is high, it schedules the opcode execution on an ALU. When the ALU completes, it will send the result over the common data bus, tagged with the #d value.
Your module's phase 2 task begins when it sees the result written by the execute module. When your module senses it, it updates Pd value and valid bit. At this point, phase 2 is over, and your module's work is done (the dispatch unit monitors the Pd valid bit). A new phase 1 begins when your module notices that the Pd valid bit has been reset to 0, and that the U bit is 1.
Assume the common data bus is synchronous, and uses the same clock that is clocking the reorder buffer state. On a rising clock edge, a one-bit VALID bus field signals that valid data is on the bus. If it is high, a 7 bit ID number bus field identifies the physical register number for the transaction (i.e. the identifiers stored in #1, #2, and #d), and the 32-bit value bus field codes the value. Note that the valid, value, and ID number wires on the common data bus will be stable on the positive edge of the clock. It will be necessary to latch the bus values, and process them with one cycle of latency.
Given this information, draw the schematic diagram for the datapath, and specify the logic equations for the write-enable signals on reorder buffer fields your module has permission to write. Do not worry about how other modules that are able to write these fields share the write-enable fields.
Please be very clear, yet short, with your design description. The highest grades will go to designs that are well-presented and which appear to be correct (there is no one right answer). If you choose to hand-draw the design and text, please be very neat and print legibly.