Welcome to the Spring 2016 CS152 web page. The course is intended to provide a foundation for students interested in performance programming, compilers, and operating systems, as well as computer architecture and engineering. Our goal is for you to better understand how software interacts with hardware, how hardware functions to provide you with the functionality you observe every day, and to understand how trends in technology, applications, and economics drive continuing changes in the field. The course will begin with basic processor design, proceed to advanced concepts found in modern products, then cover the different forms of parallelism found in applications (instruction-level, data-level, thread-level, gate-level) and how these can be exploited with various architectural features, and conclude with advanced topics on GPUs and emerging alternative architectures. We will cover pipelining, superscalar, speculative and out-of-order execution, vector machines, VLIW machines, multithreading, graphics processing units, and parallel microprocessors. We will also explore the design of memory systems including caches, virtual memory, and DRAM. Advanced topics include GPUs and alternative computational models such as neuromorphic. For more information please refer to the syllabus.
An important part of the course is a series of lab assignments using real microprocessor designs implemented in the Chisel hardware description language, and running as simulators of actual hardware. These simulators will give you an in-depth look at a variety of processor architectural techniques. Our objective is that you will understand all the major concepts used in modern microprocessors by the end of the semester.
Week | Date | Lecture | Readings 5th Edition |
Readings 4th Edition |
Assignments |
1 | Wed Jan 20 | L1: Introduction, Early Machines PDF PPT | Ch. 1, App. A | Ch. 1, App. B | |
Thu Jan 21 | Section 1: Introduction, RISC-V Tools, Abstraction Layers, Infrastructure PDF PPT |
||||
2 | Mon Jan 25 | L2: Simple Machine Implementations, Microcoding PDF PPT |
Ch 3.13 | PS 1 PDF Handout PDF Solutions PDF |
|
Wed Jan 27 | L3: From CISC to RISC PDF PPT |
App K.4 | Lab 1PDF | ||
Thu Jan 28 | L4: Pipelining PDF PPT | App. C.1-C.3 | App. A.1-A.3 | ||
3 | Mon Feb 1 | Section 2: Microcode Machines and Lab 1 Overview PDF | |
|
|
Wed Feb 3 | L5: Pipelining II PDF PPT |
App. C.4-C.6 | App. A.4-A.6 | ||
Thu Feb 4 | Section 3: Pipelining review PDF | |
|||
4 | Mon Feb 8 | L6: Memory Hierarchy PDF PPT |
App. B.1-B.2, Ch. 2.1-2.3 | App. C.1-C.2, Ch. 5.1-5.3 | |
Wed Feb 10 | L7: Memory Hierarchy II PDF PPT |
App. B.3 | App. C.3 | PS 1 due Lab 1 due |
|
Thu Feb 11 | Section 4: PS 1 Review, Lab 2 intro PDF | PS 2 PDF Solutions PDF Handout2 PDF Lab 2 PDF |
|||
5 | Mon Feb 15 | Holiday
|
|||
Wed Feb 17 | Quiz 1: ISAs, microcode,
simple pipelines Solutions PDF |
||||
Thu Feb 18 | Section 5: Memory Hierarchy PDF | ||||
6 | Mon Feb 22 | L8: Address Translation and Protection PDF PPT | App. B.4-7 | App. C.4-7 | |
Wed Feb 24 |
L9: Virtual Memory PDF PPT |
Ch. 2.4. App. B.4 | |||
Thu Feb 25 | Section 6: Translation Protection and Virtual Memory PDF | ||||
7 | Mon Feb 29 | L10: Complex pipelines, Out-of-order Issue, Register Renaming PDF PPT | Ch. 3.1,3.4-3.5 | Ch. 2.1,2.4-2.5 | PS 3 PDF Solutions PDF |
Wed Mar 2 | L11: Out-of-order Exceptions, Branch Prediction PDF PPT | Ch. 3.6, 3.8 | Ch. 2.6, 2.8 | PS 2 due Lab 2 due |
|
Thu Mar 3 | Section 7: PS 2 review; Quiz 2 Prep; Out-of-order Execution PDF | Lab 3 PDF | |||
8 | Mon Mar 7 | Quiz 2: Memory Hierarchies and
Virtual Memory
Solutions PDF |
|||
Wed Mar 9 | L12: Advanced Out-of-Order Superscalars PDF PPT | Ch. 3.7 | |||
Thu Mar 10 | Section 8: Complex Pipelines Review; Lab 3 Overview PDF | ||||
9 | Mon Mar 14 | L13: VLIW PDF PPT | Ch. 3.2,3.7 | Ch. 2.2,2.7 | PS 4 PDF Solutions PDF |
Wed Mar 16 | L14: Multithreading PDF PPT | Ch. 3.12 | Ch. 3.5 | PS 3 due | |
Thu Mar 17 | Section 9: PS 3 review, Lab 4 intro PDF | Lab 4 PDF | |||
10 | Mar 21-25 | Spring Break | |||
11 | Mon Mar 28 | Quiz 3: Complex Pipelining Solutions PDF |
Lab 3 due | ||
Wed Mar 30 | L15: Vectors PDF PPT | Ch. 4.1-4.3 (App. G) | App. F | ||
Thu Mar 31 | Section 10: Instruction Level Parallelism PDF | ||||
12 | Mon Apr 4 | L16: GPUs PDF PPT | Ch. 4.4-4.9 | N/A | PS 5 PDF Solutions PDF Handout1 PDF Handout7 PDF |
Wed Apr 6 | L17: Synchronization and Sequential Consistency PDF PPT | Ch. 5.1, 5.5-5.6 | Ch. 4.1-4.4 | PS 4 due |
|
Thu Apr 7 | Section 11: PS 4 review, Lab 5 intro PDF | Lab 5 PDF | |||
13 | Mon Apr 11 | Quiz 4: VLIW, Vectors,
Multithreading Solutions PDF |
|||
Wed Apr 13 | L18: Snoopy Caches PDF PPT | Ch. 5.2-5.3 | Lab 4 due | ||
Thu Apr 14 | Section 12: Parallel Architectures Review PDF | ||||
14 | Mon Apr 18 | L19: Directory Protocols PDF PPT | Ch. 5.4 | N/A | |
Wed Apr 20 | L20: Datacenters PDF PPT | Ch. 6 | PS 5 due | ||
Thu Apr 21 | Section 13: PS 5 Review PDF | ||||
15 | Mon Apr 25 | L21: The Future and Closing Remarks PDF PPT | |||
Wed Apr 27 | Quiz 5: Parallel Architectures Solutions PDF |
||||
Th Apr 28 | |||||
16 | Tues May 3 | Lab 5 due |
This page uses the Holy Grail Liquid-Layout: No quirks mode by Matthew James Taylor.