Welcome to the Spring 2020 CS152 and CS252 web page. This semester the undergraduate and graduate computer architecture classes will be sharing lectures, and so the course web page has been combined.

CS152 is intended to provide a foundation for students interested in performance programming, compilers, and operating systems, as well as computer architecture and engineering. Our goal is for you to better understand how software interacts with hardware, and to understand how trends in technology, applications, and economics drive continuing changes in the field. The course will cover the different forms of parallelism found in applications (instruction-level, data-level, thread-level, gate-level) and how these can be exploited with various architectural features. We will cover pipelining, superscalar, speculative and out-of-order execution, vector machines, VLIW machines, multithreading, graphics processing units, and parallel microprocessors. We will also explore the design of memory systems including caches, virtual memory, and DRAM. An important part of CS152 is series of lab assignments using real microprocessor designs implemented in the Chisel hardware description language, and running as simulators and FPGA emulators hosted in the Amazon cloud (FireSim). These simulators will give you an in-depth look at a variety of processor architectural techniques. Our objective is that you will understand all the major concepts used in modern microprocessors by the end of the semester.

CS252 is intended to provide essential background for students intending to pursue research in computer architecture or related fields, and also provides preparation for the Berkeley EECS computer architecture oral prelim examination. An important part of CS252 is reading and discussion of classic architecture papers, as well as a substantial course project.

Course Calendar with Handouts

Note: Tentative, schedule subject to change!

Week Date Lecture Readings
5th Edition
6th Edition
1 Wed Jan 22 L1: Introduction, Early Machines Ch. 1, App. A Ch. 1, App. A
Fri Jan 24 CS152 No section
2 Mon Jan 27 L2: Simple Machine Implementations, Microcoding
Mon Jan 27 CS252 No Readings Discussion
Wed Jan 29 L3: Pipelining App. C.1-C.3 App. C.1-C.3 PS 1
Fri Jan 31 CS152 Section 1: Microcode, Introduction to RISC-V tools and Lab 1 Overview Lab 1
3 Mon Feb 3 L4: Pipelining II App. C.4-C.6 App. C.4-C.6
Mon Feb 3 CS252 Readings Discussion "Design of the B5000 System", Lonergan, King, 1961
"Architecture of the IBM System/360", Amdahl, Blaauw, Brooks, 1964
Wed Feb 5 L5: Memory Hierarchy App. B.1-B.2, Ch. 2.1-2.3 App. B.1-B.2, Ch. 2.1-2.2  
Fri Feb 7 CS152 Section 2: Pipelining review      
4 Mon Feb 10 L6: Memory Hierarchy II App. B.3 App. B.3 PS 1 due at start of class
Mon Feb 10 CS252 Readings Discussion "The Case for the Reduced Instruction Set Computer", Patterson, Ditzel, 1980
Comments on the "The Case for the RISC", Clark, Strecker, 1980
"Performance from architecture: comparing a RISC and CISC with similar hardware organization", Bhandarkar, Clark, 1991
Wed Feb 12 L7: Memory Hierarchy III PS 2
Fri Feb 14 CS152 Section 3: PS 1 Review     PS 1 Solutions
5 Mon Feb 17 President's Day Holiday
Wed Feb 19 L8: Address Translation and Protection App. B.4-7 App. B.4-7 Lab 1 due
Fri Feb 21 CS152 Section 4: Lab 2 Overview     Lab 2
6 Mon Feb 24 L9: Virtual Memory    
Mon Feb 24 CS252 Readings Discussion "IBM's Single-Processor Supercomputer Efforts", Smotherman, Spicer, CACM, 53(1), 2010
"Implementation of Precise Interrupts in Pipelined Processors" , Smith, Pleszkun, ISCA, 1985 (IEEE Trans. Computer Journal version)
"Parallel Operation in the Control Data 6600", Thornton, Proceedings of the Fall Joint Computers Conference, vol 26, pp. 33-40, 1964
Wed Feb 26 L10: Complex pipelines, out-of-order issue, register renaming Ch. 3.1,3.4-3.5 Ch. 3.1,3.4-3.6 PS 2 due.
CS252 project proposals due.
Fri Feb 28 CS152 Section 5: Memory hierarchy and PS 2 review     PS 2 solution
7 Mon Mar 2 Midterm 1: (L1-L9)    
Mon Mar 2 CS252 No Readings Discussion
Wed Mar 4 L11: Out-of-order execution Ch. 3.6, 3.8 Ch. 3.6, 3.8 PS 3
Fri Mar 6 CS152 Section 6: Lab 3 Overview, Parameterizing OoO Cores
8 Mon Mar 9 L12: Branch Prediction and Advanced Out-of-Order Superscalars Ch. 3.3,3.9-3.10 Lab 2 due
Mon Mar 9 CS252 Project Proposal Discussion
Wed Mar 11 L13: VLIW Ch. 3.2,3.7 Ch. 3.2,3.7 Lab 3
Fri Mar 13 CS152 Section 7: Out-of-order Execution
9 Mon Mar 16 L14: Multithreading Ch. 3.12 Ch. 3.11 PS 3 due
Mon Mar 16 CS252 Readings Discussion "An Efficient Algorithm for Exploiting Multiple Arithmetic units", Tomasulo, IBM Journal, January 1967
"Decoupled Access/Execute Computer Architectures", Smith, ISCA 1982 (ACM TOCS version)
"The MIPS R10000 Superscalar microprocessor", Yeager, IEEE Micro 16(2), 1996
Wed Mar 18 L15: Vectors PPTX PDF Ch. 4.1-4.3 (App. G) PS 4
Fri Mar 20 CS152 Section 8: PS 3 review PS 3 Solutions
10 Mar 23-27 Spring Break      
11 Mon Mar 30 L16: GPUs Ch. 4.4-4.9 Ch. 4.4-4.9
Mon Mar 30 CS252 Readings Discussion "Combining Branch Predictors", McFarling, DEC WRL Technical Note TN-36, 1993
"Dynamic Branch Prediction with Perceptrons", Jimenez, Lin, HPCA 2001
" A case for (partially) TAgged GEometric history length branch prediction , Seznec, Michaud, Journal of Instruction Level Parallelism (JILP), 2006
Wed Apr 1 L17: Vectors II Ch. 4.1-4.3 (App. G) Ch. 4.1-4.3 (App. G)
Fri Apr 3 CS152 Section 9: Lab 4 Overview PS 4 due
Lab 4
12 Mon Apr 6 L18: Cache Coherence Ch. 5.1-5.4 Ch. 5.1-5.4 Lab 3 due
Mon Apr 6 CS252 Readings Discussion
"The CRAY-1 Computer System", Russel, CACM 1978
"Very Long Instruction Word Architectures and the ELI-512", Fisher, ISCA 1983
"A VLIW Architecture for a Trace Scheduling Compiler", Colwell et al., IEEE Trans. Computers, 1988
Wed Apr 8 L19: Synchronization and Memory Consistency Models Ch. 5.1, 5.5-5.6 Ch. 5.1, 5.5-5.6
Fri Apr 10 CS152 Section 10: Midterm 2 Review PS 4 Solutions
13 Mon Apr 13 L20: Domain-Specific Architectures and the Google TPU Ch. 6 Ch. 6
Mon Apr 13 CS252 Project Checkpoint Project update
Wed Apr 17 Midterm 2: L10-17 Ch. 5.4 PS 5
Fri Apr 17 CS152 Section 11: Lab 5 Overview   Lab 5
14 Mon Apr 20 L21: Virtual Machines Ch. 5.2-5.3 Ch. 5.2-5.3 Lab 4 due
Mon Apr 20 CS252 Readings Discussion "The Tera Computer System", Alverson et al, ICS 1990
"Shared Memory Consistency Models: A Tutorial", Adve, Gharachorloo, DEC WRL TR, 1995
"The SGI Origin: a ccNUMA highly scalable server", Laudon, Lenoski, ISCA 1997
Wed Apr 22 L22: Synchronization Primitives
Fri Apr 24 CS152 Section 12: Multiprocessor Review
15 Mon Apr 27 L23: I/O and Warehouse-Scale Computing Ch. 7 PS 5 due
Mon Apr 27 CS252 Project Checkpoint Project update
Wed Apr 29 L24: Summary
Fri May 1 CS152 Section 13: Final Review Lab 5 due
PS 5 Solutions
16 Mon May 4 No lecture - RRR Week
Wed May 6 No lecture - RRR Week
TBD CS 252 Final Project Presentations
Friday May 8 No section - RRR Week
17 TBD CS 152 Final Exam: TBD
Fri May 15 CS 252 Final Project Papers due