Note: I will eventually (probably by the weekend) update the format of this file so that it is easier to read. Sorry for any inconvenience caused. False - See Belady's Anomaly. This can occur with a FIFO replacement. One can come up with an example of page accesses that actually result in an increase in the amount of page faults; however, most systems probably use a better replacement policy and Belady's Anomaly is probably not the common case - so do not let that dissuade you from purchasing additional RAM. -------------------------------------------------------------------- True - If my access pattern consists of reading data sequentially, then by prefetching large blocks of data in advance, I can reduce the number of cache misses as the next piece of data I want to read will have already been loaded into the cache for me. -------------------------------------------------------------------- False - Hardware support means that everytime a processor access a page, it sets the use bit to 1. If no hardware support exists, you can get around this by setting each page translation's valid bit to '0.' This will cause each access to a page to initially result in a page fault. You can use this page fault handler to manually set the use bit to 1 yourself (and the valid bit to 1 as well so you don't unnecessarily page fault again). When the clock algorithm clears the use bit, you need to set the valid bit to 0 as well so that the page-fault handler can set the use bit to 1 if the page is accessed again. -------------------------------------------------------------------- False - The Clock Algorithm is an approximation to LRU; therefore, it is not guaranteed that it evicts the oldest page in memory. -------------------------------------------------------------------- False - If the oldest page in memory was recently used, the Clock algorithm will not evict it since its 'use' bit is set to 1. -------------------------------------------------------------------- True - A software TLB can be programmed to operate with any page table type. -------------------------------------------------------------------- Precise exceptions define a specific point where execution of code has stopped. No instructions have been executed after this specific point. This makes it easier to handle the exception and resume execution of the code from that point. Imprecise exceptions arise from attempts to make the 5-stage processor pipeline more efficient - out-of-order instruction execution and branch prediction are examples of optimizations that make an exception "imprecise." When an exception occurs, what if the out-of-order instruction has already been executed? What if the branch-prediction caused some change of state? All this has to be undone before we can handle the exception and resume execution from the program counter. -------------------------------------------------------------------- LRU is implemented with the use of a simple Linked List. A page that is recently used is always placed at the end of the list, meaning that the page at the front of the list is always the least recently used one. The issue with directly implementing LRU is that each memory access could involve searching for a page in the list and placing it at the end (O(n) time). If each memory access requires traversing a list of all the page table entries in the system, then this would be very slow. Of course, one could argue that the clock algorithm is also slow (since this is O(n) as well). But the clock algorithm is executed only on a page fault, and since we have to go to disk anyway to write a page out of memory and load a new page in, then running the clock algorithm incurs a very small penalty compared to swapping to/from disk and the overhead is therefore negligible. -------------------------------------------------------------------- 1) Choose an old page to replace 2) If the old page has been modified(dirty bit is set to 1), write contents back to disk 3) Change the page table entry of the evicted page and invalidate the corresponding TLB entry (if it exists in the TLB). 4) Load the new page into memory from disk 5) Update the page table entry of the newly read in page. 6) Continue thread from original faulting location -------------------------------------------------------------------- The 3rd True/False question gives an idea of the answer to this question. -------------------------------------------------------------------- Solutions to tables will be added once I format this file.