Project Resources for CS250: VLSI Systems Design

Fall 2009

ISSCC 2010 Abstracts abtracts

Intel On-Chip Networks:
A 48-Core IA-32 Message-Passing Processor with DVFS in 45nm CMOS
A 4.1Tb/s Bisection-Bandwidth 560Gb/s/W Streaming Circuit-Switched 8Ąż8 Mesh Network-onChip in 45nm CMO
A 1.2 TB/s On-Chip Ring Interconnect for 45nm 8-Core Enterprise Xeon(R) Processor
Dynamic Critical-Path Checking: Intel/ARM:
A 45nm Resilient and Adaptive Microprocessor Core for Dynamic Variation Tolerance
A Power-Efficient 32b ARM ISA Processor Using Timing-error Detection and Correction for Transient-error Tolerance and Adaptation to PVT Variation
Intel FPGA:
A 320mV-to-1.2V On-Die Fine-Grained Reconfigurable Fabric for DSP/Media Accelerators in 32nm CMOS
Gate Arrays from an Ink-Jet Printer:
User Customizable Logic Paper (UCLP) with Organic Sea-of Transmission-Gates (SOTG) Architecture and Ink-Jet Printed Interconnects
Chip-to-Chip Inductive Coupling:
2Gb/s 1.8pJ/b/chip Inductive-Coupling Through-Chip Bus for 128-Die NANDFlash Memory Stacking
An 8Tb/s 1pJ/b 0.8mm2/Tb/s QDR Inductive-Coupling Interface Between 65nm CMOS GPU and 0.1!m DRAM

Non-blocking Caches:

Lockup-Free Instruction Fetch/Prefetch Cache Organization. David Kroft. Proceedings of the 8th International Symposium on Computer Architecture (ISCA-8) 1981. paper
Cache Refill/Access Decoupling for Vector Machines. Christopher Batten, Ronny Krashinsky, Steve Gerding, and Krste Asanovic. Proceedings of the 37th International Symposium on Microarchitecture (MICRO-37) 2004. paper

Instruction Caches:

Reducing Set-Associative Cache Energy viaWay-Prediction and Selective Direct-Mapping. Michael D. Powell, Amit Agarwal, T. N. Vijaykumar, Babak Falsafi, and Kaushik Roy. Proceedings of the 34th International Symposium on Microarchitecture (MICRO-34) 2001. paper
Way Memoization to Reduce Fetch Energy in Instruction Caches. Albert Ma, Michael Zhang, and Krste Asanovic. Workshop on Complexity-Effective Design, at 28th International Symposium on Computer Architecture (ISCA-28) 2001. paper

On-chip Interconnect:

Design Tradeoffs for Tiled CMP On-Chip Networks. James Balfour, William J. Dally. Proceedings of the 20th International Conference on Supercomputing (ICS'06) 2006. paper
Low-Latency Virtual-Channel Routers for On-Chip Networks. Robert Mullins, Andrew West, and Simon Moore. Proceedings of the 31st International Symposium on Computer Architecture (ISCA-31) 2004. paper
On-Chip Interconnection Architecture of the Tile Processor. David Wentzlaff, Patrick Griffin, Henry Hoffmann, Liewei Bao, Bruce Edwards, Carl Ramey, Matthew Mattina, Chyi-Chang Miao, John F. Brown III, and Anant Agarwal. IEEE Mirco 2007. paper

Memory Controller:

Memory Access Scheduling. Scott Rixner, William J. Dally, Ujval J. Kapasi, Peter Mattson, and John D. Owens. Proceedings of the 27th International Symposium on Computer Architecture (ISCA-27) 2000. paper
Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems. Onur Mutlu, and Thomas Moscibroda. Proceedings of the 35th International Symposium on Computer Architecture (ISCA-35) 2008. paper
Memory Controller Optimizations forWeb Servers. Scott Rixner. Proceedings of the 37th International Symposium on Microarchitecture (MICRO-37) 2004. paper