CS 250: VLSI Systems Design
- Semester lab grades can be seen
for grading mistakes and always mail both
Will and Randy about them.
- For those who are turning in their final project late, please
be sure to get it in by Tuesday, noon.
- Get new cadencesucksbig from .../final/bin.
Also, you may recopy Cadence library rcore if you have problems
- End of semester request for student
feedback by Prof. Wawrzynek. Reponse would really be appreciated!
- Get new .cdsinit from .../final/dotfiles.
- Get new full.VCMD from .../final/netlist.
Appendix A of Lab 9 reviews some of the things covered in the last
- The files in .../labs/final/netlist/ Makefile and
nocntl.VTRAN have been updated. The check target in the Makefile
should now work.
- The file c_cpucntl.inc in the RTL has been updated. Download it
- I forgot to mention something rather important in lecture. You
need certain dotfiles in your root directory for cadence to extract
correctly. Some of you may already have good ones, but just to be
sure, please get all the dotfiles from .../labs/final/dotfiles.
- You should probably get the new RCORE RTL from Will for the final project.
To do so, run /disks/test0/a/cns/cs250/labs/final/get_rcore from your
NOW account in an empty directory. If (and only if) you are done with lab 8, please mail Will with
the subject line `lab8done' to get the password that you must enter.
Will is trying to get his procmailrc setup to reply automatically,
but it refuses to work, so please be patient as he hunts around for
- Nasty Bug in RTL: This bug rarely shows up, but it is really
awful when it does. Both modules rcore and sram receive
a signal called clkin, which they both invert to make phi.
This is bad because, while both modules use phi as its clock,
the two phi's are not synchronized to one another. Because the
behavior is unpredicatable on Verilog, the simulator may fail when
it is uninstrumented, and then may work fine when you add in statements
to trace variables to find out what went wrong. The way to fix this
is to generate phi as the inverse of clkin in the module
all, and then pass phi to both rcore and sram.
- Prof. Bose will no longer be responding at mmc.net since he no longer
works there. A new email address will be given very soon. Meanwhile
please send midterms, hwks, and questions to firstname.lastname@example.org
- One more lab7 mistake: signals branch and branchb should
have been in On_critical instead of Op_critical.
- 4-4-97, 4:35pm
- Update to lab7 just made again. Please reload cpucntl.script.
- 4-4-97, 11:40am
- Update to lab7 just made. Please reload cpucntl.script.
- Regarding lab 7: It will be out whenever Will finishes
it, which is probably not earlier than Thursday.
- An important message from Prof. Bose
regarding the midterm cheating.
- The computer account form is processed. It is the
same password as your instructional account.
- The license file has been updated.
- Lab 7 will be going out on Monday. Enjoy the Spring Break.
- Please turn lab1-6 in by next Friday (March 28) if you have not already.
- The cs250 class has access to the NOW cluster.
Here is how.
List of past announcements
- B. K. Bose
- Will Chang
- Michal Siwinski
Time and Place:
- Tu 11:00-12:30, F 9:00-10:30 310 Soda Hall
- Lab Lecture
- Th 11:00-12:30 Place TBA
- Office Hours
- TBA (Prof. Bose)
- TBA (Will)
The lab exercises are designed to teach a commercial CAD tool
design flow, reinforce concepts from the lectures, and look at
processor design at the circuit and layout level. The framework for
the labs is a custom MIPS implementation. This implementation
includes an ISA simulator, an executable RTL description, a
transistor-level netlist, and complete layout. As a course project,
students will be provided with an incomplete netlist and layout and
asked to first complete, and then improve the design.
The project is spread out over the semester and interleaved with
tutorial material. A weekly lab lecture will cover the basic
principles behind the CAD tools and review processor design.
Tools demos will be held in the lab lecture or made available online.
Each lab is graded on a scale of 1 to 10 and assigned a weight proportional to the number of weeks it is scheduled for. Lab grades are 45% of your final grade
In each lab, you will be asked to turn in feedback on working conditions such as computer resources, the time it takes to complete the assignment, cad tools, and the effectiveness of the assignment. This constitutes 10% of your lab grade.
List of machines available in 347 and 349 Soda Hall.
Free machines. Thanks to
Lab Lecture Notes:
- Design Representations and Flow
Little T0 Tour
- VLSI Libraries Incorporated
- Spring 96