|Thur Aug 30||N/A||No reading, prepare for prereq quiz.||N/A|
|Thu Sep 6||Tue Sep 11||
"A new approach to the functional design of a digital computer",
R.S. Barton, AFIPS Conference Proceedings, Vol. 19, 1961,
"Design of the B5000 system", W. Lonergan, P. King, Datamation, Vol. 7 No. 5, May 1961, pp28-32.
For further detail, see also B5000 Descriptor
"Architecture of the IBM System/360", G. M. Amdahl, G. A. Blaauw, F. P. Brooks Jr., IBM J. Res. Develop. Vol. 8, No. 2, 1964
Assignment #1, Part A
Burroughs B5000 vs IBM 360
Write a maximum of one page summarizing and comparing the two architectures.
|Thu Sep 6||Thu Sep 13||
"The case for the reduced instruction set computer",
D. A. Patterson and D. R. Ditzel, SIGARCH Computer Architecture News,
Vol. 8, No. 6, 1980, pp25-33.
"Comments on 'The case for the reduced instruction set computer' by Patterson and Ditzel", D. W. Clark and W. D. Strecker, SIGARCH Computer Architecture News, Vol. 8, No. 6, 1980, pp34-38.
Assignment #1, Part B
RISC vs CISC
Write a maximum of half a page summarizing the RISC vs CISC debate.
|Thu Sep 13||Tue Sep 18||"Limits of Instruction-Level Parallelism", David W. Wall, pages 1-35 only||
Write a maximum of one page summarizing the conclusions of the study. Include a discussion of at least one flaw you believe the paper might have.
|Thu Sep 20||Tue Sep 25||
"The Cray-1 Computer System", Richard M. Russel, CACM
21(1), January 1976.
"The Cydra 5 Departmental Supercomputer: Design Philosophies, Decisions, and Trade-offs", B. Rau et al, IEEE Computer, January 1989
Using the assigned papers and Appendices F and G, compare the VLIW and vector approaches to improving performance. Which do you think is more effective, and why?
|Sun Oct 28||Tue Nov 6||
"Shared Memory Consistency Models: A Tutorial", Sarita
Adve, Kourosh Gharachorloo, DEC WRL Techreport 95/7, September 1995.
"Multiprocessors should support simple memory-consistency models", Mark Hill, IEEE Computer, August 1998
Summarize the arguments for and against providing sequential consistency at the ISA level. What memory model do you believe should be provided at the hardware level? The language level?