In this course we will discuss the basic foundations of
reconfigurable computing, survey the successes (and failures) in architectures
and mapping tools, and survey a wide range of applications. The objective of the course is to form an
understanding both how to architect reconfigurable systems and how to apply
them to solving challenging computational problems. The course will be structured as occasional lectures from the
instructor and visitors used to set the stage for conference paper reading and
class discussion, along with independent work on projects. Each student is expected to read the
assigned papers, participate in the class discussions, provide in-class project
status reports, and a final project presentation.
The primary objective of work in reconfigurable computing is to search for a better alternative to the computing model followed in traditional processors. It is well documented that microprocessors are becoming less and less efficient in their use of silicon resources -- resulting in less performance than possible and more power consumption than necessary. Modern microprocessors attempt to achieve high performance by extracting instruction level parallelism and simultaneously issuing multiple instructions. As market forces and applications demand more performance, the necessary circuitry to keep up has become increasingly complex to the point of diminishing returns. The inefficiencies of conventional microprocessor architectures has also lead to inefficient multi-processor systems. In recent years, conventional microprocessors have been able to continue to offer performance and power consumption improvements in spite of architectural deficiencies only because of heroic efforts to improvement the IC manufacturing processes.
Reconfigurable computing is a relatively new area (partially
pioneered here at Berkeley in the mid 1990's).
Its basic promise is that FPGA's (field programmable gate arrays), and other
devices reconfigurable at the logic-gate level, can be an efficient hosts for a
wide variety of applications. The
structure of a computation can be mapped directly to logic circuits, avoiding
the inefficiencies of instruction set interpretation found in conventional
computers. Furthermore, because the
low-level flexibly of reconfigurable devices allows them the adapt to a wider
range of parallelism models and application needs, on real applications they
yield a significantly higher percentage of peak performance.
Early work in the field showed that recofigurable devices
offer a significant advantage in peak computational density over conventional microprocessors. Encouraging results have been demonstrated
in a number of areas including cryptography, signal processing, and searching---achieving
10-100x computational density over more conventional processor solutions. The promise of this approach is to achieve
near custom-chip level performance with the flexibility of software programmability
in a solution that scales naturally with problem size and with improvements in
technology. This idea is already
revolutionizing the way we design and program a wide class of applications. However, as this approach is a major shift
in the standard model, questions remain about how broadly applicable these devices
are, how they should be designed, and how they should be integrated into
computing systems.