** 10/8/09 - Notes for CS 294-48 ** Today: further review of BHPL and breaking designs into patterns Important to note non-goal of BHPL, only mapping and structure, not application itself Every unit is an FSM - A purely combinational component is just one state - You could even describe a MIPS processor with an enormous FSM Handling control issue from last week - since every unit is a FSM, describe it (factor it) in the clearest way - slides describe: structural decomposition or control + datapath Breaking a design into Control + Datapath is a pattern - Since all systems can be represented as an FSM, key is to factor out control state - FSM based on control state summarizes the controller - Datapath state isn't as interesting, and it makes the effective FSM huge - Build datapath our of components with succinct known functionality Can break control into inter-transaction and intra-transaction - Example: network router, a 'transaction' is process of routing an input packet to an output port - Transaction is hierarchical, a transaction at one level can be broken into smaller ones at lower levels BHPL in Practice - taking a design down to RTL through vertical slice - each pattern maps from one layer to layer below it - highest layer is mapping from application to high-level (like UTL) - unit->rtl pattern layer - for each unit, how do you make RTL - can be hierarchical (more layers in between) Purpose of BHPL is to be technology independent - Getting architecture and structure right has bigger impact than RTL tweaks - Actual design process will involve taking an application to RTL, and then iterating Next week we will break down examples, starting with Henry's crypto accelerator