---------------------------------------------------------------------- October 29 Fall 2009 - CS294-48. Next week: people start picking patters -> winding down. VGA LCD Controller: (Shaoyi) -------------------------------------------- "Sink" for the Video project (Chris C) - dumping video to an LCD panel. Arbitration between a number of specialized processors - color, cursor, Wishbone, the LCD itself. Host writes/reads registers (status, configuration) Double buffering. The address generator takes information from the control registers (base addr for cursor, color map, etc). Address generation - a video counter (separate resetting counts for vertical and horizontal location on the image) with horizontal and vertical sync outputs. Cannot quite assume it is a counter - likely an FSM-style implementation. The frame buffer and the double buffering scheme is shown *within a channel* - a suggestion has been made that Excessive hiding too much detracts from the meaning - too much abstraction carries no information. Tangent : The new MacOS 10 - all applications share video memory! Tangent : Is Wishbone actually used anywhere? Whose standard is it? During the inactive parts of the video frame, the memory bandwidth is used to transfer cursor data, etc. Many paths in the system are time-multiplexed to improve utilization of channels due predictably periodic video traffic. This circuit is heavy on communication patterns Other notables: Double buffering (again - 3rd example in this group). TEMAC on the Xilinx Vertex 5 : Chris (interchangable with Ilia, apparently). -------------------------------------------- Diagram shown originally meant to instruct a user new to the circuit - very close to UTL. Two different primitives at play: EMAC - implemented in silicon. TEMAC - Coregen-generated soft core utilizing the EMAC. Auto-negotiation: communication between the TEMAC and the (one or multiple) MDIO-enabled PHY (off-chip). (MDIO is an I2C-like synchronous serial protocol) Flow control embedded in the 802.3 standard. A special status packet allowing a sink to temporarily mute the source. Address filter registers: small array of registers (simple CL, rather than indicies into memory). The mac address itself enncodes status packets, etc. All state collected within the datapath is collected and exposed to the FPGA fabric via muxes. Includes 8b/10b encoding (in PCS/PMA sublayer), interfaced with a GTP. MII : 10/100Mb ethernet GMII : 10/100/1000/Mb The EMAC block runs *without* a GTP for an MII interface. GMII requires a GTP transceiver. UTL (See slides). Careful not to use the controller symbox L in UTL - more or less reserved for leaf-level diagrams (synchronous controller). ___ /__/ Clocks can be thought of as flow control signals. Since links in UTL imply flow control if needed, Disembodiesd arrows do not fit with the UTL paradigm. One of the main patterns here is time-multiplexing of links (cable cost, etc). ------------------------------------------------ ISCA deadline - 16th. Patterns workshops will start around then.