Computer Science 294-57: Scalable Shared Memory Systems for Manycore Microprocessors

Spring 2010

Prof. Krste Asanović

Meetings: Thursday, 5:00-7:00PM, 405 Soda

The advent of massively parallel single-chip microprocessors places extreme demands on the accompanying memory system. The challenge is to support a productive programming model at high performance but low power dissipation. This class will explore the design space for single-chip multiprocessor memory systems, including issues such as scalable coherence protocols, consistency models, memory-based synchronization and communication primitives, software-managed memory hierarchies, private vs. shared vs. hybrid last-level caches, on-chip and off-chip interconnects, main memory systems, DRAM, non-volatile RAM, flash, phase-change memory, workloads, and evaluation techniques. The goal of this class is to develop a proposal for future microprocessor memory systems to guide research in this area. The class is intended for graduate students performing research in computer architecture, parallel programming systems, or manycore operating systems.

Class assignments for 2 units of credit will consist of critical analyses of assigned research papers, participation in class discussions, and contribution towards a group-authored white paper on future multiprocessor memory systems. Students taking the class for 4 units will undertake a semester-long research project.

Course Calendar with Handouts

Subject to Change.

Week Date Meeting Agenda Assignments
1 Thu Jan 21 No meeting.  
2 Wed Jan 27 Introduction  
3 Thu Feb 4 Modern server memory systems Modern Servers: Power-7, AMD Magny Cours, Intel Nehalem-EX
HotChips/IEEE Micro 2010
4 Thu Feb 11 Discussion of DRAM papers 8Gb 3-D DDR3 DRAM using Through-Silicon-Via Technology Kang et el., IEEE JSSCC, January 2010
No writeup for following slide sets, only for 3D DRAM paper above
Future Mobile Memory for Mobile and Consumer Devices, Lionel Saives, ARM, 2009
Main Memory Technology Direction Kevin Kilbuk, Micron, 2007
The Future of Memory Storage, Dean Klein, Micron, 2007 (First part only, not flash)
5 Thu Feb 18 Flash Memories Flash Memories: Successes and Challenges, Stefan K. Lai, IBM J. Res. & Dev., July/Sep. 2008
No writeup for following articles, only for flash paper above
Three-bit-per-cell NAND products entering main stage, Young Choi, EE Times, 1/21/2010
Intel, Micron 25nm NAND, Intel News Release, 2/1/2010
(Samsung 30nm DRAM Announcement, Samsung, 2/1/2010)
6 Thu Feb 25 Phase-Change Memory Architecting Phase Change Memory as a Scalable DRAM Alternative, Benjamin Lee, Engin Ipek, Onur Mutlu, Doug Burger, ISCA-2009
No writeups for following articles, only for ISCA paper above
Non-Volatile Memory Technologies: The Quest for Lower Cost, Stefan Lai, IEDM 2008
A 45nm 1Gb 1.8V Phase-Change Memory, Villa et al., ISSCC-2010
7 Thu Mar 4 Discussion of Group White Paper 1-Page Project Proposals Due (for 4-unit students)
8 Thu Mar 11 On-Chip Interconnect Design tradeoffs for tiled CMP on-chip networks, James Balfour, William Dally, ICS 2006
Research challenges for on-chip interconnection networks, Owens et al., IEEE Micro 2007
9 Thu Mar 18 Tiled CMP NUCA Schemes Near-Optimal Cache Block Placement with Reactive Nonuniform Cache Architectures, Hardavellas et al, IEEE Micro Hot Picks Issue, Jan/Feb 2010
Virtual Hierarchies, Marty and Hill, IEEE Micro Hot Picks Issue, Jan/Feb 2008
No writeups for following background articles, only for papers above
Victim Migration: Dynamically Adapting Between Private and Shared CMP Caches Zhang and Asanovic, MIT Technical Report MIT-CSAIL-TR-2005-064, October 2005.
Integration Challenges and Tradeoffs for Tera-scale Architectures, Azimi et al., Intel Tech. Journal, August 2007
10 Thu Mar 25 No Class Spring Break
11 Thu Apr 1 Discuss Group White Paper  
12 Thu Apr 8 No Class  
13 Thu Apr 15 Discuss Group White Paper  
14 Thu Apr 22 Discuss Group White Paper  
15 Thu Apr 29 Discuss Group White Paper  
15 Extension: Tue May 11 (@9AM) Deadline for contributions to Group White Paper