CS 61C Homework 9 Spring 2004 Submit your answer by 11:59 p.m. on Wednesday April 28. 1. Consider the following program segment: add $5, $6, $7 lw $6, 100($7) sub $7, $6, $8 Suppose that this code runs using a pipeline that detects hazards and stalls if a hazard arises. Count how many cycles will be needed to execute this code, and display each instruction's progress through the pipeline in a format similar to that of Figure 6.3. You can submit this online as ASCII art, so Figure 6.3 would look like this: LW $1 F D A M R LW $2 F D A M R LW $3 F D A M R The letters FDAMR stand for Fetch, Decode, ALU, Memory, Register. I only showed enough of each instruction to make it clear which is which. 2. Consider the following program: move $5, $0 Sum: lw $10, 1000($20) addu $5, $5, $10 addiu $20, $20, -4 bne $20, $0, Sum Suppose that this code runs using a pipeline that neither stalls nor forwards on hazards. Add as few ``no-op'' instructions as necessary to prevent data and control hazards, and display the progress through the pipeline of execution of the first six original instructions (i.e., up through the LW of the second iteration of the loop) in a format similar to that of Figure 6.3. You may assume that there is enough hardware to test registers, calculate the branch address, and update the PC during the second stage as explained on page 442. You may also assume that register values may be read in stage 2 of the pipeline as they are written by an earlier instruction in stage 5. 3. Reorder the instructions in the loop from exercise 2 to minimize the number of ``no-ops'' while preserving correctness. Then redisplay the progress through the pipeline of the first six original instructions, as in exercise 2.