// Behavioral level CPU blocks
//
// J. Wawrzynek
// Nov 2001

//Behavioral model of 32-bit Register:
// positive edge-triggered,
// synchronous active-high reset.
module reg32 (CLK,Q,D,RST);
   input [31:0] D;
   input 	CLK, RST;
   output [31:0] Q;
   //
   reg [31:0] Q;
   always @ (posedge CLK)
     if (RST) Q = 0; else Q = D;
endmodule // Reg32

//Behavioral model of 32-bit adder.
module add32 (S,A,B);
   input [31:0] A,B;
   output [31:0] S;
   reg [31:0] 	 S;
   //
   always @ (A or B)
     S = A + B;
endmodule // Add

//Behavioral model of Read Only Memory:
// 32-bit wide, 256 words deep,
// asynchronous read-port,
// initialize from file on positive
// edge of reset signal, by reading
// contents of "text.dat" interpeted
// as hex.
//
module ROM (RST,address,readD);
   input RST;
   input [31:0] address;
   output [31:0] readD;
   reg [31:0] readD;
   //
   reg [31:0] memArray [0:255];
   always @ (posedge RST)
     $readmemh("text.dat", memArray);
   always @ (address)
     readD = memArray[address[9:2]];
endmodule // RAM

//Behavioral model of Random Access Memory:
// 32-bit wide, 256 words deep,
// asynchronous read-port if RD=1,
// synchronous write-port if WR=1,
// initialize from hex file ("data.dat") on positive
// edge of reset signal, 
// dump to binary file ("dump.dat") on positive
// edge of dump signal.
//
module mem (CLK,RST,DMP,WR,RD,address,writeD,readD);
   input CLK, RST, DMP, WR, RD;
   input [31:0] address, writeD;
   output [31:0] readD;
   reg [31:0] readD;
   //
   parameter  memSize=256;
   reg [31:0] memArray [0:memSize-1];
   integer    chann,i;
   always @ (posedge RST)
     $readmemh("data.dat", memArray);
   always @ (posedge CLK)
     if (WR) memArray[address[9:2]] = writeD;
   always @ (address or RD)
     if (RD) 
       begin
         readD = memArray[address[9:2]];
         $display("Getting address %h containing %h", address[9:2], readD);
       end
   always @ (posedge DMP)
     begin
	chann = $fopen("dump.dat");
	if (chann==0)
	  begin
	     $display("$fopen of dump.dat failed.");
	     $finish;
	  end
	for (i=0; i<memSize; i=i+1)
	  begin
	     $fdisplay(chann, "%b", memArray[i]);
	  end	     
     end // always @ (posedge DMP)
endmodule // mem

//Behavioral model of 32-bit wide 2-to-1 multiplexor.
module mux32 (in0,in1,select,out);
   input [31:0] in0,in1;
   input 	select;
   output [31:0] out;
   //
   reg [31:0] out;
   always @ (in0 or in1 or select)
     if (select) out=in1;
     else out=in0;
endmodule // Mux

//Behavioral model of 5-bit wide 2-to-1 multiplexor.
module mux5 (in0,in1,select,out);
   input [4:0] in0,in1;
   input 	select;
   output [4:0] out;
   //
   reg [4:0] out;
   always @ (in0 or in1 or select)
     if (select) out=in1;
     else out=in0;
endmodule // Mux

//Behavioral model of register file:
// 32-bit wide, 32 words deep,
// two asynchronous read-ports,
// one synchronous write-port.
// Dump register file contents to console
// on positive edge of dump signal.
//
module regFile (CLK,wEnb,DMP,writeReg,writeD,
		readReg1,readD1,readReg2,readD2);
   input CLK, wEnb, DMP;
   input [4:0] writeReg, readReg1, readReg2;
   input [31:0] writeD;
   output [31:0] readD1, readD2;
   reg [31:0] readD1, readD2;
   //
   reg [31:0] array [0:31];
   reg 	      dirty1, dirty2;
   integer    i;
   always @ (posedge CLK)
     if (wEnb)
       if (writeReg!=4'h0) 
	 begin
	    array[writeReg] = writeD;
	    dirty1=1'b1;
	    dirty2=1'b1;
	 end
   always @ (readReg1 or dirty1) // use posedge dirty1 to run just once
     begin
	readD1 = array[readReg1];
	dirty1=0;
     end
   always @ (readReg2 or dirty2)
     begin
	readD2 = array[readReg2];
	dirty2=0;
     end
   always @ (posedge DMP)
     for (i=0; i<32; i=i+1)
       $display("r%0d:%h", i, array[i]);
   initial
     array[0]=0;
endmodule // regFile

//Sign extender from 16- to 32-bits.
module signExtend (in,out);
   input [15:0]  in;
   output [31:0] out;
   reg [31:0] 	 out;

   always @ (in)
     out = { in[15], in[15], in[15], in[15],
  	     in[15], in[15], in[15], in[15],
  	     in[15], in[15], in[15], in[15],
  	     in[15], in[15], in[15], in[15],
  	     in[15:0] };

endmodule // signExtend

//32-bit Shift left by 2
module leftShift2 (in,out);
   input [31:0]  in;
   output [31:0] out;
   reg [31:0] 	 out;

   always @ (in)
     out = {in[29:0], 1'b0, 1'b0};

endmodule // leftShift2

//Behavioral model of ALU:
// 8 functions and "zero" flag,
// A is top input, B is bottom, according
// to P&H figure 5.19.
//
module ALU (A,B,control,zero,result);
   input [31:0] A, B;
   input [2:0]  control;
   output 	zero;
   output [31:0] result;
   //
   reg 		 zero;
   reg [31:0] 	 result, C;
   always @ (A or B or control)
     begin
	case (control)
	  3'b000: // AND
	    result=A&B;
	  3'b001: // OR
	    result=A|B;
	  3'b010: // add
	    result=A+B;
	  3'b110: // subtract
	    result=A-B;
	  3'b111: // set on less than
	    // old version (fails if A is negative and B is positive)
	    // result = (A<B)? 1 : 0;
	    // if A and B have the same sign, then A<B works;
	    // if A and B have different signs, then A<B if A is negative.
	    begin
		C = A-B;
		result = (A[31]^B[31])? A[31] : C[31];
	    end
	endcase // case(control)
	zero = (result==0) ? 1'b1 : 1'b0;
     end // always @ (A or B or control)
endmodule // ALU