CS61C - Spring 2005 - Lab 08
Finite State Machines

Problem 1

Consider the design of a finite state machine (FSM) with two 1-bit inputs (clk and CE), and one 2-bit output (X). clk is the clock signal and CE is the "count enable" signal. While CE=1, the FSM behaves as a "binary counter", i.e. its output cycles through the pattern 00, 01, 10 11, 00, moving from one output value to the next on each positive edge of clk. If CE = 0 the output value remains unchanged.

Note that FSM has no reset input signal. You can assume that it starts up in any legal state.

Sketch the state transition diagram that represents the behavior of this FSM.

Problem 2

Draw the waveform diagram for the first 5 iterations of the following FSM (Refer to page 5 of Monday's handout "CS61c: State Elements: Circuits That Remember"). What operation does this FSM perform? Write a simple function in the language of your choice which returns the value stored in "Register 2" as a function of the number of clock ticks since the FSM started.

Note: T-add, T-clk-to-q and the clock period are exactly the same as on the example on page 5. I.e., T-add is double T-clk-to-q, which are bothmuch less than the clock period.

Initial State: Register 1 holds '1' and register 2 holds '0'.