CS 61C Lab 10
Spring 2005

Goals
In this lab exercise you will gain experience designing and simulating a simple sequential logic circuit. It will give you practice using Logisim for logic simulation and (we hope) an appreciation for the issues involved in designing, testing, and debugging sequential logic circuits.

P&H section B.10 (copy can be found here). Refer to the Logisim Website or last week's lab for a refresher on Logisim.

Working with partners
If you work with a partner on these exercises, make sure that you both understand all aspects of your solutions. Where you split work among partnership members, expect your lab t.a. or lab assistant to ask you to explain the work of your partner.

Background
Appendix B in P&H present a description of a circuit used to control a traffic light. Your job in this lab is to implement and test the traffic light controller in Logisim.

The details of the traffic light controller finite state machine are explained in P&H. You should follow that specification with one modification. Add an input signal
called RST. Asserting this signal should "reset" the controller to the NSgreen state (on the next positive clock edge) regardless of its current state and the value of the other inputs. Otherwise your circuit should be identical to the one described in the book.

Exercise 1
Create a sub-circuit that implements the next-state combinational logic for the trafic light.

Exercise 2
Create a circuit that implements the traffic light controller. This module must include an instance(s) of your next-state combinational logic and a flip-flop to hold the current state. Test it with a couple of input cases.

Exercise 3
Devise a scheme to test your circuit. You want some way to test all possible inputs and verify that they produce the correct output. Try to come up with something more clever than manually flipping the inputs and verifying the outputs.

Exercise 4
Stepping back from Logisim for the moment, we'd like to analyze this circuit. If each of our primitive gates (defined here as a basic gate in Logisim) has a propagation delay of 1ns, Clk-to-q of the DQ flip-flop is 3ns, and the setup and hold times for the flip-flop are each 2ns answer the following questions: What is the total delay of your combinational logic that determines next-state? What is the fastest clock speed we could run this system at with stable results?

Once all of this is complete, show off the results to your Lab TA or Lab Assistant for checkoff.

Having done this lab …
We expect that, having done this lab assignment, you will understand the use of a flip-flop to store state and will be familiar with the pattern of splitting a finite state machine into the controller, which maintains the current state, and the next-state and output combinational functions.