CS 61C Quiz - Week 13

Current time: Thu Jan 18 23:19:40 2018

Deadline: Sun Apr 27 23:59:59 2008

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Question 1:

Suppose that a page contains 4 Kbytes.  A virtual address and a
physical address are both 32 bits wide.  Here is the TLB:

    Virtual page #    Physical page #
  -------------------------------------
0 |     0x00678     |      0x27       |
1 |     0x01234     |      0x543      |
2 |     0x12345     |      0x200      |
3 |     0x45678     |      0x5        |
  -------------------------------------

Convert the virtual address 0x12345678 into a physical address.

Question 2:

Patterson and Hennessy list some sample performance figures
for TLBs and caches.  An example appears in the table below.

                TLB             cache
size            32 wds          4096 wds
block size      1 word          1 word
organization    fully assoc     direct-mapped
miss rate       1%              12%

Note that the TLB, which is significantly smaller than the cache,
has a significantly better miss rate. Briefly explain why.

Question 3:

How does the addressing mode of memory change how you simulate a cache?
For example, a byte addressed memory vs word addressed memory.

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